Please explain PXI5112 sync example

[olifri]

I need to synchronize the time stamp counters on 4 PXI5112. I took a look into the sync example and have some difficulties to understand:

Both Master and slave are configured to send (resp. receive) a sync signal on the RTSI0. But when exactly will the Master generate a pulse? Does it have to receive a trigger signal (Maybe software trigger or immediate trigger?) There is no dataflow dependeny between the two ConfigureClock VIs. What happens if the Master gets configured before the slave.Is the master generating a sync pulse that no one will receive because the slave is yet not configured to receive a sync pulse.

Does sync mean that the timestamp counters are aligned to exact the same value? Do I have to take into account the Tr
iggerToRTSI resp the RTSIToTrigger properties to compensate for propagation on the RTSI lines? I need to align all TimeStampCounters to minimal skew possible. How much is it?

[Jochen]

Oliver,

in the example you mention two RTSI lines are used. RTSI0 carries the 10 MHz clock to synchronize the board clocks using PLL. It really doesn't matter which board is configured first to synchronize on this signal. RTSI1 carries the trigger signal generated by the master to start the acquisition on the slave.

As there is a board specific propagation delay you can add an additionial propagation delay in this example. Before starting your real measurements you should determine this delay by applying the same signal to both boards and aligning them with this parameter.

All this information and more can be found in the online help of the vi, in the descriptions in the diagram and in the online help of the front panel elements.

Best regards,

Jo
chen Klier
NI-Germany
[SRQ 212122]