IF-RIO
Can I put two FPGA TO HOST FIFO(DMA) write in a Single Clock Timed Loop?
Hi,
I am making several tests on my pipelined Single Delay Feed Back FFT implemented in FPGA.
The first step is that I tried to verify that my code succeed to transfer the data from HOST to FPGA. In the first attached picture, this SCTL read the IQ data (triggered as the INput Data switch comes from False to True), and then write it into two FIFOs in the next iteration. the "FFT Data" is local FIFO, (I have another SCTL in which the FFT functions and the FFT Data is read). "testFIFOinput" is FPGA to HOST DMA, (set to be "Never Arbitrate" in the options for wirte).
The second attached picture, is part of the Host VI code. I am sorry that it is a little bit messy. Essentially, after the IQData is read, I manually switched the GettestFIFO to be true and trigger the event in which the testFIFOinput is read.
Now here comes the problem.
I could observe that the FFT is functioning( I had another DMA FIFO to read the output of the FFT SCTL block, and I got the data I want from this DMA FIFO), which indicates the the data is corretly written to the local "FFT Data". However, my Host VI fails to read out any data from the "testFIFOinput". Array 4 which is used to store the data from "testFIFOinput" is always empty.
My question is : Can I put two FPGA TO HOST FIFO(DMA) write in a Single Clock Timed Loop? If I could, then, could you please shed some light on where I might made a mistake. Please let me know if I need to supply more details.
Thanks in advance.
David
I am making several tests on my pipelined Single Delay Feed Back FFT implemented in FPGA.
The first step is that I tried to verify that my code succeed to transfer the data from HOST to FPGA. In the first attached picture, this SCTL read the IQ data (triggered as the INput Data switch comes from False to True), and then write it into two FIFOs in the next iteration. the "FFT Data" is local FIFO, (I have another SCTL in which the FFT functions and the FFT Data is read). "testFIFOinput" is FPGA to HOST DMA, (set to be "Never Arbitrate" in the options for wirte).
The second attached picture, is part of the Host VI code. I am sorry that it is a little bit messy. Essentially, after the IQData is read, I manually switched the GettestFIFO to be true and trigger the event in which the testFIFOinput is read.
Now here comes the problem.
I could observe that the FFT is functioning( I had another DMA FIFO to read the output of the FFT SCTL block, and I got the data I want from this DMA FIFO), which indicates the the data is corretly written to the local "FFT Data". However, my Host VI fails to read out any data from the "testFIFOinput". Array 4 which is used to store the data from "testFIFOinput" is always empty.
My question is : Can I put two FPGA TO HOST FIFO(DMA) write in a Single Clock Timed Loop? If I could, then, could you please shed some light on where I might made a mistake. Please let me know if I need to supply more details.
Thanks in advance.
David
