Filtering with IF-RIO

[wired]

Hi everyone,

I'm currently evaluating IF-RIO to determine if it is usable for a filtering application.  I would like to be able to input two separate signals on A/D channels 0 and 1, and apply an identical bandpass filter to each channel.  The filter bandwidth would be about 300Khz with a 10.7MHz center frequency.  Linear phase in the passband would be desirable.  The filtered data would then be upconverted again and output to the 2 DACs.  This would not be I/Q input data, but 2 different signals.

It's my understanding that some filtering can be performed by the DDC, but I'm really unclear about how to set it up. I'm hoping to avoid doing any filtering in the FPGA - that would probably make this a much more difficult task.

I was hoping there might be some example VIs, or some supporting tools for easily setting up the system to do this, but I haven't found anything.  I'm not an EE, so I'm finding it all a bit confusing.  Does anyone know if there's a way to use the DFD Toolkit to aid in programming the IF-RIO's DDC filters?  Any advice or information would be much appreciated - I have very limited time to figure all of this out - less than 2 weeks.

Thanks,

Kevin

[Mauricio Capistran-Garza]

Have you looked at the "Frequency Translation" Example. That example takes an input signal on AI0 channel at the specified center frequency and then transmits it back out through AO0 channel at the new center frequency (which can be the same). The filters for both the DUC and DDC have linear phase, so that should be a good starting point. The examples only does it for one input and one output, but if it works, then it should be fairly simple to update the FPGA VI to do it for 2 in and 2 out.

Also, the example uses a bandwidth of 10 MHz, so you will need to update the Host VI. For the bandwidth of 300 kHz I think you might be lucky. If you select the decimation in that example to "100", the filter that it's implemented actually has a 300 kHz bandwidth. This is the only filter that it's not 0.4 of the IQ rate, but seems like would work great for your application. To do that, open the block diagram and replace the "8" constant wired to the "ni5640R ADC Configure DDC VI" (fourth VI from left to right) by a "100" constant. Then, you will also need to change to update the "4" constant wired to the "ni5640R DAC Configure for Quadrature Mode" (which is inside the "Transmit Frequency" case of the event structure) to a "50".

- Mauricio

[wired]

Mauricio,

Thanks for the advice.  I've modified the code to handle two channels in and out, and will be performing some testing soon.  FYI, the example VI that I had did not list a constant of 100 for the DDC configuration - I had to add it.  I did see that the called routine handles a value of 100, so I guess it was an oversight in the example programming.

[wired]

Q1) Is there any documentation anywhere on what the IF-RIO VIs actually do?  For instance, ADC Config DDC has a decimation factor parameter.  It seems that this causes a number of input filtering parameters to change.  What are the actual effects of changing this value?  I would like to further reduce the passband of the input, but am unclear on how to do that.  The VI Help says: "This VI configures the DDC decimation by writing a pre-recorded set of filters."  I could use more detail...

Q2) Is there any way to use the DFD Toolkit to aid in programming the DDC filters? If not, are there other tools for helping configure the DDC at a lower level that the ADC CONFIG DDC VI?

[Mauricio Capistran-Garza]

A1)The Configure DDC VI sets all the filters and decimation factors in the DDC. It's a pretty flexible DDC with a many configurable elements. So the best documentation would be to look directly at the datasheet for the part (AD6654: http://www.analog.com/en/prod/0%2C2877%2CAD6654%2C00.html). For other documentation references look at this posting: http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=140

A2) Yes, it's possible. However, the part has many elements to configure so it ends up being complex to do.

[wired]

Mauricio,

Thanks for the response. So I guess there's no documentation on what the provided VI does at the various decimation factors...  I did take a look at the data sheet, which is why I asked if there was an easier way to figure out the DDC configuration 🙂

Next question - I modified the Frequency Translation example to use two channels.  In a nutshell, I added two more timed loops for the second channel, and created two more FIFOs.  The program seems to work OK, but the problem I'm seeing is this:

I am feeding a sinusoidal waveform at 10.7MHz from a SigGen into both A/D channels.  My VI is set for a 10.7MHz receive and a 10.7MHz transmit frequency. My DDC constant is 100 and the DAC constant is 50.  The 2 DAC channels are going to 2 scope channels.  Each time I start and stop the VI, I get a different phase relationship between the DAC0 and DAC1 outputs.  I can change the SigGen frequency within the passband, and this is causing a phase change between the 2 DAC outputs; however, sometimes the phase change is very small within the passband (say 30-45 degrees), and sometimes it is much larger (180 or more).  I must be missing something in the initialization, or maybe there needs to be some kind of syncronization between the 2 channels?  Any advice on how to make this more deterministic would be appreciated.

Kevin

[wired]

Re: filter design - It looks like Analog Devices has a software package to do filter design for the AD6654.  Here's the link:

http://www.analog.com/en/content/0,2886,760%255F788%255F24275,00.html

[Mauricio Capistran-Garza]

Kevin,

If you are interested in phase synchronized inputs and outputs it's a bit more complicated. This is the list of things you have to do:

In the project:

1) Add the "RTSI Clk" to the project. You can do that by right-clicking the FPGA Target and selecting New >> FPGA Base Clock.

In the FPGA VI:

1) Only use one loop for the input and one loop for the output. Choose the ADC 0 Clk as the clock for the input loop and the DAC 0 Clk as the clock for the output loop.

2) Change the clock that is running the Configuration Loop from the "Configuration Clk" to the "RTSI Clk". The RTSI Clk is synchronous to the DAC and ADC clocks, so doing the configuration in this clock will allow you to reset both ADCs and DACs simultaneously in order to get them synchronized.

In the Host VI:

1) Before doing any ADC or DAC configuration, put a Read/Write node and write a TRUE to "Config.ADC Simultaneous Programming" and "Config.DAC 0 Simultaneous Programming". By doing this, any configuration that you set to ADC 0 will be set to both ADCs (same will happen with the DACs).

2) On the Host VI, delete any VIs that are doing any explicit configuration to ADC 1 or DAC 1.

3) Change the DAC configuration VIs to use Profile 1 instead of Profile 0.

4) Once you are done with DAC configuration, but before you write the "Start" control on the FPGA, do a DAC Reset. Resetting the DAC will reset the phases of the NCOs to zero, thus assuring that both DACs will have the same phase. It's important that you are using Profile 1, because doing a Reset to the DAC resets Profile 0.

[wired]

Mauricio,

I did what you said, and I no longer have the varying phase offsets with frequencies if I do NOT perform the DAC0 Reset.  If I perform the reset, the DACs do not provide any output.  I am using a write node to set the Config.DAC 0 Reset after the DAC0 Config IQ VI in the Transmit Frequency case.  If this is set to FALSE, I get DAC output with a phase offset between channels, but it does not very when I change my input frequency on the sig gen.  If I set it to TRUE, I get no DAC output. 

[wired]

Forgot to mention - I am passing a Profile of 1 into the DAC Config IQ VI just before doing the DAC Reset.  I also tried adding a Profile Sel element prior to the DAC Reset element on the write node, but it made no difference.