Filtering with IF-RIO

[Mauricio Capistran-Garza]

Hi Kevin,

I should have mentioned that there is a ni560R Reset DAC VI that you should use. Try using that VI and let me know how it goes.

- Mauricio

[wired]

OK, I did two Write Node VIs for the DAC, the first one sets Reset TRUE, the second one sets Reset FALSE.  I assumed it was a one-shot find of thing.  I still had the fixed phase offset, also I tried adding two  ADC0 Reset nodes to toggle the reset after the ADC NCO VI in the Receive Frequency case.  I ran the Host, but the VI timed out on a FIFO read operation.  I set both of the ADC0 Resets to FALSE, and when I ran it the two DAC outputs were phase-aligned.  Can you give me any more information on this?

Thanks,

Kevin

[wired]

Oops, just saw your last post, Mauricio.  Will try that instead.

[wired]

Mauricio,

That did the trick! I am in phase and unaffected by input frequency changes.  However, after making this change, I am unable to run both the FPGA vi and the Host VI.  The FPGA VI runs OK the first time I start up LabVIEW, but when I tried to start the Host, I got a Communications Error dialog.  When I stopped the FPGA VI and tried to restart it, I got the same error for the FPGA VI.  Is there something I need to configure in the Host VI?

[wired]

I tried things in a different order, and I am able to get it to work, just not as reliably as in the supplied example.  Sometimes my Spectrum graph changes shape after the FPGA VI starts.  Sometimes I click on the Run button for the FPGA while the Host is running, and nothing happens.  When I stop the Host VI, the FPGA VI starts running.  I still get sporadic communications error when trying to start.

[Mauricio Capistran-Garza]

Hi Kevin,

You should never run the FPGA VI by iteslf. The first subVI in the Host VI opens and runs the FPGA for you. I can't really comment on the behavior you're seeing because I'm not sure what exactly happens when you explicitly run both.

- Mauricio

[wired]

OK - I'm ready to take the next step for our application.  Thanks to your help, I've been able to produce the matched filters with the response that we are looking for.  Now we need to do some signal processing and conditioning in real time, and I'd like some advice on the best way to accomplish this, because it seems like there may be different was to do it.

What I would like to do, is periodically (somewhere around 100 -1000 Hz rate) determine the phase difference between my two input signals, and adjust the phase of one signal to match that of the other.  Once the phase is adjusted, I'd like to match the amplitude of the two signals.

It seems like there are hardware features that could perhaps be taken advantage of in doing this.  The NCO can be programmed with a phase offset, the DAC has a Scale Factor, and there is AGC circuitry available (which might be able to perform the amplitude matching for me?

Right now, I am using the Simultaneous Programming feature of the board to create the deterministic, matched phase on startup.  Will I be able to deterministically adjust the phase using the phase offset of the NCO, i.e. can this happen 'on the fly'?  Or is there a better way to do some of these things, such as in the FPGA?

Regards,

Kevin     

[Mauricio Capistran-Garza]

Hi Kevin,

First of all, let me just warn you that I've never tried this before, but it should work. To get the phase aligned I can think of two options:

1) As you mentioned, the ADC has a phase offset, which could be written any time. The first thing that you will need to do, is set the "simultaneous programming" control to "false" in order to avoid setting this value to both ADCs. Then, to set the phase offset there is no VI to do that, so you will need to create your own. A simple way to do that is to open a VI named "ni5640R ADC 68 - NCO". That VI writes all the NCO configuration registers, including the phase offset. Save that VI with a new name and strip it to only write the phase offset. The other tricky thing is that, as stated in the datasheet, "the value in the register is loaded into the phase accumulator of the NCO block every time a start sync or hop sync is received by the channel." So I'm guessing you will need to generate a start sync after writing that register. To do that you can call the VI "ni5640R ADC 05 - Soft Sync". As I said before, I've never done this, so I'm not sure there aren't any more gotchas.

2) The second option would be to change the phase of the data in the FPGA (AFTER it's been downconverted). To do that you first need to figure out the current phase and magnitude of the signal. To get the phase you will need to use a 1/x loop-up table to divide Q/I and then an Arctan loop-up table to get the phase. Then you would need to add the desired offset to the phase.  Then, using a sine look-up table and the magnitude you should be able to create the I and Q values again. This approach will take considerable more time to develop but should work.

About the magnitude compensation, you're right about the DAC Scale Factor. You will also need to set the "DAC simultaneous programming" to "false" and then you'll also need to create your own VI to set the Scale Factor. The easiest way to do that is to use the VI "ni5640R DAC Register Write". The Scale Factor offset for Profile 1 is 0x0C. You can also use the VI "ni5640R Convert Scale Factor to Binary" to get the binary version of a value between 0 and 1.992 (which is the supported scaling range).

About the AGC circuit, you're right that there is one in the ADC. Unfortunately, I don't have much experience using it, so I can't give you any recommendations on that regards. There is a VI named "ni5640R ADC A0 - AGC" which configures the AGC, but I'm not sure what all the parameters are; you would need to read the documentation in the datasheet and experiment yourself.

Hope this helps

- Mauricio

[tigr]

Hello Mauricio

I tried to close Costas loop by the first mechanism you proposed (set ADC phase offset then SoftSync), but without success. May be the reason lies in bit <2> Clear NCO Accumulator? Do you know the exact difference between start sync and hop sync?

I still hope the proposed mechanism should work

Thanks in advance

[tigr]

hi

I'd like to simplify the question. We have Analog Input and Output example with minor additions (see attached). The baseband input is simply 16x(1+0*i). I see a single point on constellation plot and its polar angle varies each time I start and stop host vi. I expect the cheange of the polar angle of the point after altering the DDC phase on the fly, but nothing occurs.

Thanks in advance