DFD can design LPF FIR filter and rational resample coefficients AND generate FPGA code for you. The code is a non-stop loop, using FIFO for input and output, so you can put it in your LV FPGA code.
Best part, in DFD, there are step by step examples. So you don't have to learn the AD 6654 from a 88 page UM.
However, programming thr 6654 is also a good approach if you understand how it works. The trick is in the 5640R ADC Filter Set vi. I designed 100 based decimation filters in step of 2x up to 25600, and for each decimation, I generated a set of filters with 80%, 60%, 35% and 17% passband BW. Bad news is, it is an IP of my company and you need to buy it from my company.
