HDL Interface Node (UsingFilterCore.vi) and "timing constraint" error when compiling

[JerryAL]

I'm trying to use the HDL interface node in LV8 FPGA with a PCI-5640R and had the "timing constraint" error when compiling my VI, however, the same VI was successfully compiled on a CRIO-9104, it seems the FPGA on PCI-5640R is not good as the one on CRIO-9104, or I'm not using it right. could you please kindly help me out?

I tested it with the sample code downloaded from NI website

( http://zone.ni.com/devzone/conceptd.nsf/webmain/456722DDDE17986A86256E7B0065EE6F ) which demonstrates using an IP core for a filter. To simplify it, I only keep the HDL Interface Node and the While Loop (see "UsingFilterCore.vi" in attached zip file), and then I created 2 projects including this VI (1 for CRIO-9104, in sub folder "CRIO-9104", the other for PCI-5640R, in sub folder "IFRIO 5640"). When opening the 2 projects separately in LV8.0 and selecting the VI for compile, the one for 9104 passed and the other failed. Here I attach the source code, error message screenshot and the NIReport from MAX, hope you can reduplicate the problem.

Can you help me out？ Thanks very much !

Message Edited by Jerry_L on 03-26-2006 09:28 PM

Message Edited by Jerry_L on 03-26-2006 09:29 PM

[JerryAL]

It appears that the Xilinx Filter uses a synchronous reset in its design.  There are 2 things you need to do to make this design work.

1)  The core gen component in the dev zone article is for the FPGA on the cRIO and R series platform.  This is different than the FPGA on IF-RIO.  You need to recreate the Core for the FPGA on IF-RIO (xc2vp30-ff896-5).  I already did this using the coefficients from the Dev Zone article.  Use attached edn file.

2) You need to remove the RST from the design.  Go to the code tab of the HDL node.  Under architecture delete the line RST: In std_logic;.  Under begin remove the line RST => reset,.

This will remove the reset from the filter design.  According to the filter IP Core documentation this reset is a synchronous reset that does not do what we thought it originally did.

Message Edited by Jerry_L on 03-26-2006 09:40 PM

[russian]

Hi Jerry,

I'm just tried to make all these steps by myself (http://zone.ni.com/devzone/cda/tut/p/id/3516). I have generated FIR filter using Xilinx ISE and got *.VHD file which was going to use in HDL Node.

In the Parameters tab of the HDL Interface Node configuration dialog, double-click in the Names column to add parameters. Create parameters as shown below.

Next, switch to the Code tab. Notice that your parameters now appear in the entity section. To complete the next two sections of code, you will need to refer to the filt.vhd file that you generated earlier and interface the filter core to the LabVIEW FPGA execution system.
1. The first problem I met was integrating VHDL code from earlier generated *.VHD file to CODE tab in properties of HDL Node. Content of entity section in *.VHD is not the same that in your attached file. Please check it in attached files. I'm sure this is the main reasen of problem.

Next, switch to the External Files tab. Click the Add File button and select the filt.edn file that you created earlier. This is the EDIF netlist file that you generated earlier.
2. I have no idea where can I get it and when during filter generation using Xilinx ISE it was generated too. How can I get it? I had to use your attached file filt.edn.

3. After that I have made the same schematics like you have in your VI FPGA and try to run. But I've got two error messages:

HDL Interfave node: enable chain not handled. Details: Refer to the documentation for the correct assignments for the enable_out output from your HDL code.

HDL Interfave node: output not handled. Details: Right-click the node, select Configure to open the Configure HDL Interface Node dialog box, and use the Code tab to handle all output parameters. 

Actually I need to model FIR filter:

Bandwidth 200-600 Hz

Sampling 8 KHz

Attenuation 80 dB

That's why I tried to follow all these steps by myself to understand how does it work.

Thanks a lot.

Nikita

 

[russian]

Hi Jerry,

In addition send to you filter.vhd which was generated with Xilinx ISE.

Best regards,
Nikita

[Tunde_A]

Hi Nikita,

LabVIEW uses dataflow paradigm, hence you will need to enforce the dataflow from the upstream data to the HDL node and the downstream data from the HDL node. The enable signals (enable_in and enable_out) allow you define when all the inputs to the HDL node are valid to begin execution and when the outputs are valid for the next block diagram node.

The enable signals must be defined to prevent any code generation error. The LabVIEW FPGA Help provides information on enable chain signals and controlling execution of HDL node within and outside a Single Cycle Timed Loop (SCTL).

Tunde A

[Nikita]

Hi Tande,

Thanks for the repliy)

It seems I understood what is the problem, but I couldn't solve it yet. I have couple more questions:

We have the workable project for example attached to this Jerry's reply "IFRIOHDL1" with given specifications. What file does include this specifications of this filter after generation FIR filter using Xilinx ISE? I mean if I want to change these onces in this project what files I should use and what I should change in HDL node for it? HDL code in code tab in HDL Node or *.edn in extarnal files tab. Actualy I didn't have any generated file with *.edn format. And as far as I understood hdl language in code tab there are no any filter specifications. There are only Execution Control and Enable Chain Signals for HDL Code which is acceptable for any specifications. Am I right?

Thanks,

Nikita