Hi Siddu
Sorry, I had wanted to create an example showing what must be done, but current workload has kept me from getting the time to do so.
The basic issue is to create and transfer your waveform data from the host as fast as or faster than the data is consumed by the DAC on the NI 5640R module, or we get an underflow. The best way to get the program running is to start out with a very slow generation /IQ rate and work out the kinks of the code itself. This rate may actually be slower than the actual rate required. (BTW, what IQ rate do you need for your application?)
Here are a few tips, instructions that you need to do.
Host side
1. For the Host to Target/ni5640R DMA process, you should configure the DMA buffer on the host computer to be relatively large (especially if you are going to be running at a rate that taxes the PCI bus and other components of the system). You can do this by using an Invoke Node on the DMA buffer and configuring it for a good size number. For a 1 MSps IQ rate, 500,000 samples might be a good number to start with. The important point is that you want to keep the host buffer with as much data as possible so that the NI5640R will always get data when it needs it.
2. When you start downloading waveform data to the DMS buffer, you should fill up the DMA buffer (and the buffer in the FPGA, more on that later) before the DAC actually starts generating. We need to “prime” the system so to speak. When the system is primed, then the host code must send a signal to the FPGA that the DAC should now start generating.
3. When downloading data while the DAC is generating, the process should be to check the available space periodically. When the space is available to a write of data of a certain chunk size, then do the DMA write. You can do this by writing an empty array of data size zero with a timeout of zero. This will immediately return with a number indication how much space is available in the DMA buffer. When the value is greater than your chunk size, write a new set of data to the DMA buffer. The polling action should happen fairly quickly, at least quicker than trying to write a number of samples to the DMA buffer and finding out that there isn’t enough room.
Chunk Size: Chunk size is system dependant. Writing 1 sample of at a time to the DMA buffer will be really slow. Writing extremely large arrays to the DMA buffer at one time will be slow as well. Large arrays can be unwieldy in terms of the OS allocating space for the arrays and slow the process down as well. A happy medium should be found, which is dependent on the amount of RAM on your computer, the type of processor, and any other applications that you may be trying to run at the same time.
FPGA:
1. There should be two loops, 1. The loop reading data from the DMA FIFO and passing data to a Local FIFO. 2. A loop reading the data from the Local FIFO and then to the DAC Write node.
The loop reading data from the DMA FIFO should run as fast as the fastest DAC IQ rate. This loop can always run at this rate regardless of the rate you configure the DAC IQ rate. If the DMA FIFO is empty, then there is no write to the Local FIFO, in this case, you are probably headed to an underflow state and starve the DAC of data pretty quickly. If the Local FIFO is full and the new IQ sample from the DMA buffer can’t be written, on the next iteration of the loop, skip reading a new sample and try to rewrite the current sample to the Local FIFO. Do this until there is room in the Local FIFO.
The DAC loop is simplye taking data out of the Local FIFO and sending it to the DAC.
In each loop, you should create indicators which will signify whether the FIFOs have underflowed for an error condition. If the Read DMA FIFO to Write Local FIFO loop is definitely running faster than the DAC loop, if the Read Local FIFO in the DAC loop will provide the best error location for an underflow. When the Read Local FIFO is empty, an underflow has occurred and this should set a flag so that the Host program errors out.
The flags should be able to be reset.
The Local FIFO should also be as large as possible to ensure that the DAC has data. There might be some cases where the OS goes off and does something which prevents the transfer of data from the Host DMA buffer to the FPGA. This will allow the DAC to have a reserve of data to generate until the process of transferring data to the FPGA resumes. This is another reason that the Read DMA FIFO and Write Local FIFO loop should run twice as fast as the DAC loop so that if the Local FIFO starts running low, the system can refill it up faster than data is being consumed. You can run the Read DMA FIFO loop off the RTSI clock running at 50 MHz.
These are the basics and should get you started.
Jerry
