How to configure the dac to interpolating mode?

[sidda]

Hi Jerry,
I got this code from NI.
I got a doubt regarding card, If I have given 70 MHz IF with 20Mbps QPSK Modulated data at the input. Then t card will work or not. Because my system specifications are data was up to 20Mbps.

Siddu

[JerryAL]

Hi Siddu

That depends, if your IQ rate is 25 MSps, that gives you a 20 MHz bandwidth. Whether or not it will work for you will depend on how many samples per symbol you need and the filters you need to demodulate to determine what the actual data bit rate will be.  I think it can be done, but that opinion doesn’t take into account any specific modulation scheme you need to implement.

You might want to look at this example and see what you can get out of it.  It is based upon the “MT PSK Transceiver(with FFT Spectrum).vi”.  It does a back to back loop from CH AO0 to AI0.

ftp://ftp.ni.com/support/rf_segment/demos/ifrio/Transceiver/

Jerry

[philippe_w]

Siddu,

The name ADC_0_Port_A_AGC is perhaps a bit misleading. The upper 13 bits are not used (you would probably want to mask them out). The lower 3 bits indicate which DDC channel inside the ADC was used to produce the current IQ pair. This is something that would probably only be useful to someone who is doing custom configuration of the ADC through its Microport interface and is using different settings on different channels. This value would let them identify and sort the IQ pairs as they are read from the port.

~Philippe

[sidda]

Hi Jerry,

I had gone through the ADC FILTER TOOL!.vi, which you have given to me. In that I am not able to understand one thing, that is, I think depending upon the decimation rate the filter coefficients will be changed. But in that vi I didn't find like that. Suppose, my control input is DDC Demation(2 to 2048), then the CIC, DRCF,MRCF filter coefficients and order will change or not?

Siddu       

[sidda]

Hi Jerry,

Thanks for your response. As per your suggestion, I downloaded the qpsk transceiver code. When I am trying to open this code it is asking these two VI's.

1. MT EbNo Calculation(PSK).Vi

2. MT Calculate EbNo.Vi

Please provide these two vi's. I will test this code.

Thanks and Regards

Siddu 

[JerryAL]

Hi Siddu

The group that made the QPSK example is updating it for me to LV 8.5.  It will be a few more days. I will post it when they have it ready.

I have to wait on the other question.  I’ve forwarded your question on to a person who might know.  I have not gotten that down into the details of the ADCs yet.

J

[JerryAL]

Hi Sidda

This is what I got from my associate.

“This VI of course was never intended for public consumption, as least not without some tidying up first. The customer will need to realize that the VI is NOT smart. It's strictly a manually-operated VI, wherein you have to know what the restrictions of the chip are. To some extend it informs or reminds the user of the limitations, such as where it reminds you the max rates in and out of FIR1, FIR2, HB1, and HB2 and where it computes the number of taps available at each of the filters. But you're free to take that information from above, ignore it, and ask for as many taps and filters as you like; when you try to actually program the chip with too many taps it'll just cut off the list. Probably no fire will spew out to the top of the chip.

Sometimes the Remez exchange subVI fails to converge, and that's reported at the bottom of the panel where it shows the filter parameters and computations. Ironically, the solution is often to give it more difficult requirements, such as tightening the passband flatness or increasing the stopband rejection. Or tightening the transition band. On the other hand, sometimes you just have to ask for one fewer tap. I didn't spend a lot of time trying to figure out how to feed and care for the Remez exchange. It works about 90% of the time.

This particular VI only creates a flat passband response. If you want to have some other response, like a raised-cosine response, you'll have to multiply that in with the weighting data in the block diagram. Shouldn't be too hard to figure out.

No warranty expressed or implied. Your mileage may vary. See dealer for details. Some restrictions apply.”

The use of the VI is supported not supported by National Instruments, and as I said, I do not know enough of the details to use it, much less explain how it should be used.  I provided it so that if you wish to go farther than what NI supports, it may help you.

Jerry

[sidda]

Hi Jerry,

I tried a lot for continuous generation in interpolating mode. But, it was giving error. Please help me in this issue. If it works I will prove my system to our customer. Please help me, I am awiting for your response.

Thanks and Regards

Siddu

[sidda]

Hi Jerry

 How are you?

I am siddu, after a long time i mailed to you.

I am getting one error in 5640r when I configured for second input channel i.e ADC!.

I am attaching that error with this mail.

Please help me in this issue. I am awiting for your response.

Siddu

[JerryAL]

Hi Sidda

Can you modify the shipping Input and Output example to use CH1 on the ADC?  You'll need to add the ADC1 clock to the project, change the IO node in the FPGA VI from ADC0 to ADC1 and change the SCTL configuration to the ADC1 clock.  The host only needs a simple change to convert it from ADC0 to ADC1.

WHat version of LabVIEW and ni5640R are you using?

Jerry