IF-RIO
Megasample CompactRIO analog input module
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The 9221 is currently the fastest analog input module available from NI. To my knowledge there aren't any third party modules available that will provide you a faster input rate.
The protocol between the FPGA and module is defined by the module developer. So it can be SPI, but you can also define your own custom protocol. You can use up to 8 signal lines for this communication.
The details of module communciation are documented in the CompactRIO Module Development Kit.
Hi,
I have never tried this before, but in theory (I think) it should work. Since each NI 9201 module can only go as fast as 800KS/s, what you can do is use a pair of modules to acquire each of your two signals (not sure if just one pair can handle both signals; I think it will be pretty close to 1MS/s so it may do the trick). The idea is that the acquisitions are off by half a cycle. That is, at t=0us you acquire from AI0 on ModA, at t=1us acquire a point from AI0 on ModB, at t=2us acquire a point from AI0 on ModA and so on. Then you just either directly write to the same FIFO from both loops (although I didn't write the VI that way, I think it should work), or you later interleave the data points.
You may understand better the idea by looking to the attached image or the attached VI.
Has anybody tried this before with no luck? Any reasons why this wouldn't work? Signal integrity issues?
JMota
PS. I think I have my numbers off by a factor of two. You want to wait for 1us before you start acquiring data from Module2, and then continously acquire data from the modules at 500KS/s (2us wait). In <b>my</b> ideal world, it seems that you should be able to go up to 1.6MS/s with two modules.
I have never tried this before, but in theory (I think) it should work. Since each NI 9201 module can only go as fast as 800KS/s, what you can do is use a pair of modules to acquire each of your two signals (not sure if just one pair can handle both signals; I think it will be pretty close to 1MS/s so it may do the trick). The idea is that the acquisitions are off by half a cycle. That is, at t=0us you acquire from AI0 on ModA, at t=1us acquire a point from AI0 on ModB, at t=2us acquire a point from AI0 on ModA and so on. Then you just either directly write to the same FIFO from both loops (although I didn't write the VI that way, I think it should work), or you later interleave the data points.
You may understand better the idea by looking to the attached image or the attached VI.
Has anybody tried this before with no luck? Any reasons why this wouldn't work? Signal integrity issues?
JMota
PS. I think I have my numbers off by a factor of two. You want to wait for 1us before you start acquiring data from Module2, and then continously acquire data from the modules at 500KS/s (2us wait). In <b>my</b> ideal world, it seems that you should be able to go up to 1.6MS/s with two modules.
Message Edited by JMota on 11-14-2006 06:41 PM
