Question about the development flow with NI5640R!

[xy_se]

Hi all,
I am Sunny,new to NI 5640R. Before posting this, I have read related posts carefully and I just want to make some concepts sure.
I will choose FPGA module rather than the API driver to develop my project.
I read  a post by Jerry talking about using 5640R to generate AM modulated signals. It seems that Jerry recommended using the input and output.VI example as a start point.
Well, as my understanding, the flow shall be like this(in my case, I will use ASK instead of AM):
1. the user provide raw bit-stream pattern(message)
2. use NI measurement toolkit on the host PC to generate the ASK modulated signal (I/Q waveform)based on the bit-stream in step 1
3. refering to input and output.VI example, and download the I/Q waveform generated in step 2 to the FPGA (through the DMA channel)
4. after the NCO frequency-translates the I/Q waveform to IF (15-35MHz according to 5640R spec.), output the IF signal from AI0 port to RF front-end(I'll use NI 5610 upconverter)

This is my first 4 steps to realize a transmitter, after this I will move on to the receiver side.

Another concern is that the software in my Lab might be too old( Labview 8.0, FPGA module 8.0, 5640R1.0, Modulation Toolkit 3.0), I want to update the software to LV 8.5,LV FPGA 8.5 and 5640R1.2. My question is :
1. If I only update these 3 software, does Modulation Toolkit 3.0 still work?
2. I will go on to install RFSG 1.3.1, and RFSA 2.0.7(latest), is there any order I shall follow to install all these stuff? Do I have to uninstall LV8.0 at first?

So, can anyone give me a confirmation that this is OK?

Thanks!!


帖子被xy_se在05-16-2008 09:40 PM时编辑过了

帖子被xy_se在05-16-2008 09:41 PM时编辑过了

[Vinay_Kumar]

Hi Sunny,

Your steps towards building a transmitter are right. Here are some things to note
a. If you are trying to stream the data/ continuously modulated on a continuous stream of bits, then it is better to pack the bits, DMA these packed bits, modulate them on the FPGA and then send it to the DAC port.
b. However, if you want to modulate only a set of bits and write this waveform onto the memory block on the 5640R and replay the waveform again and again. Here the DMA happens only once. This method will be helpful for quick testing of your demodulators.
c. I would recommend you to first prototype all these on the PC. Write proper test benches which will acertain the functionality of your FPGA code.

You can look at the On-Off Keying modulator which is on IPNet  under the RF and Communication section.

Answer to your other question
1. Modulation Toolkit 3.0 should work fine with LV 8.5.
2. Order of installation:
Uninstall Modulation Toolkit 3.0
Install LV 8.5
Install RFSG, RFSA drivers
Install Modualtion toolkit 3.0

Install LV FPGA 8.5
Install 5640R 1.2 drivers

You need not uninstall LV 8.0

Cheers,
Vinay


Message Edited by Vinay Kumar on 05-19-2008 04:02 AM

[xy_se]

Thanks very much for the reply, I have installed Labview 8.5 and the related stuff also gone through the provided examples. I have one doubt and one question:
1. The doubt is:
At the beginning of each project, the FPGA resources (I/O, clock, etc)are added to the project in the project explorer and I clicked the property of DAC IQ clock, its frequency is fixed(e.g. 25MHz). Later when various interpolation values are applied to the DAC, the DAC IQ clock shall be changed. But, when I clicked the property of DAC IQ clock again, its frequency is still the original one. So I guess the user doesn't have to care about the clock in the property, it will be changed automatically. Am I right?

2. My question is: Since the compile time is quite long each time, is there a way to simulate the FPGA code before compilation and download?( Namely, the counterpart of pre-simulation in conventional FPGA design) .Is there any getting started tutorial about this on NI website?


Thanks again!

Sunny


帖子被xy_se在05-21-2008 11:01 AM时编辑过了

[Vinay_Kumar]

Sunny,
1. The frequency of the DAC IQ clock which you see when you right click on the clock is only required for compilation. However, the value of the DAQ clock changes as per the configuration from the host and will not be reflected on the DAC clock property.

2. One of the good things about LV 8.5 is that you can test your FPGA code as it is*. This means that LV simulates the functionality of the FIFO, memory blocks.
    * ADC I/Q input, DAC I/Q pins, HDL node need to be replaced with equivalent code.
How to test FPGA code in LV?
a. Open a new VI. Place the sub VI that you need to test. Make sure this VI does not have ADC/DAC pins, HDL nodes.
b. Replace single cycle timed loop with normal While loop, to improve the speed of execution of the VI.
c. Add code to generate your test vectors.
d. Add code to validate your output!

--Vinay

[xy_se]

Thanks very much!

As for the simulation, I tried another method. I turn on the emulator option in the project, and just click and run my VIs, it seems working. Is this method right?

Regarding to your reply, if I understand correcly, it is:
 I build a new VI and put the FPGA VI inside. Then replace all the timed loops in the FPGA VI with while loops.

But if I have two timed loops driven by different clocks(namely, they run at different speeds), how can I simulate this just using while loops? Shall I add the time delay to them?

[Vinay_Kumar]

Yes, you can use the emulator option. But the input data will be random.
If you want to test the functionality / debug your code, the method mentioned before is better since, you can give user defined test vectors as input.

Regarding simulation of two timed loops using different clocks, you can have a mod n counter to simulate the edge of the clock.
Its a good practice to write the processing blocks in one loop, which runs at a much higher clock rate (RTSI) and the acquisition/ generation in ADC/DAC clock domains.

--Vinay