Working at much lower sample rate.

[david uang]

Hi, I am using PCI 5640R to do Amplitude Modulation with 25k Symbol per seconds. I am trying to work with sampling frequency at 200kHz, i.e. 8 samples per symbol.
I have a timed loop configured at the DAC_IQ_clock (2MHz), which is the lowest frequency I can get.
I tried with a flat sequency with loop timer in the first frame.  But then I realize that I still need to put shift register or feedback on the timed loop(2MHz). I am trying to use the shift register or feedback to implement a FIR for which I hope to be working at 200kHz.

How could I have a timed loop or similar structure working at 200kHz in FPGA?

Many Thanks.

David

[Mauricio Capistran-Garza]

Hi David,

The DAC sampling rate is 200 MHz. The Digital Upconverter (DUC) will take data at a slower rate and interpolate it to reach 200 MHz. However, the maximum interpolation that the DUC can do is 252, which means that the slower it can take in data is ~793.65 kHz. So you will not be able to work with a samping frequency of 200 kHz unless you build an interpolating filter in the FPGA that takes the data from 200 kHz to something larger than 800 kHz. A "simple" way to work around that problem is to use 40 samples per symbol (therefore using a sample rate of 1 MS/s).

I don't understand your comment about having "a timed loop configured at the DAC_IQ_clock (2MHz), which is the lowest frequency I can get." I have a couple of questions regarding that comment:

1) How are you configuring the DAQ_IQ_clock rate? Are you using a DAC configuration VI in your host application to do the configuration (which is the correct way of doing it)? or are you right-clicking on the clock in the project and setting the "Nominal Frquency"? Configuring the "Nominal Frequency" only tells the VHDL compiler what is the highest rate that you plan on running that clock (for timming constraints), but doesn't actually configure the clock at that rate.

2) Why do you say that 2 MHz is the lowest frequency?

The way I recommend to go about doing processing in the FPGA is to separate your code in a processing loop and a generation loop. The generation loop is the one that runs in a Single Cycle Timed Loop (SCTL) configured to use the DAC_IQ_Clk. The rate of this loop will determine you sampling rate and indirectly (depending on how many samples per symbol are you using) your symbol rate. For your processing, since it's not very time demanding, you could use a regular loop (instead of a SCTL). By default, regular loops run on a 20 MHz clock. So if the generation loop is consuming data at 1 MS/s, you will have 20 clock cycles to complete your processing. If that is not enough, you might want to change the processing loop to be a SCTL as well. Then, you would send data from the processing loop to the generation loop using a FIFO.

- Mauricio

[david uang]

Hi, Mauricio

  Thank you for your help! It is much clearer to me now.
  I am using the DAC configuration VI to configure the rate.  I made a mistake in taking 50 as the maxim interpolating factor. However, I am still a little bit confused about the DAQ_IQ_clock as I wrote in my previous post:
  The REF clock is the VCXO which is at 200MHz. Therefore, if we use as 50 as the interpolating factor, the DAQ_IQ_clock is 2*200/4/50=2MHz. Isn't it? Which means my SCTL will be running at 2MHz?

  Thanks!

David

Message Edited by david uang on 01-18-2007 07:38 PM

[Mauricio Capistran-Garza]

Hi David,

You're right. The DAC_IQ_Clk will be running at 2 MHz. However, you have to remember that you have to write your IQ data interleaved. So it takes 2 clock cycles to write each IQ sample (That's why you have to multiply by 2 in the equation). Therefore, your effective IQ rate is 1 MS/s

- Mauricio

[david uang]

Hi, Mauricio

   I just realized your point after spending some time on the Digital Filter Design tookit. By seperating, you mean that my processing loop is not synchornized to the generation loop.
   How much resource does the FIFO consume?
   I am now considering using the following scheme: For transmition design a root raised cosine filter with 8 Sample per symbol, then do the interpolation. My reason is that if I were to do it on 40 Sample for Symbol, my root raised cosine filter might consume a lot of multipliers and adders. Do you think which appraoch sounds more promising?
   Thank you.

David/Dayu

[JerryAL]

Hi David

I don’t have an exact value for the FIFO resources, but there is a little over head in terms of the amount of resources that you calculate by the size of the FIFO times the data type.

Here are some additional links on the topic.

Utilization of LabVIEW FPGA Structures/Functions/Data Types on an FPGA
http://zone.ni.com/devzone/cda/tut/p/id/4733

FPGA Utilization Table
http://sine.ni.com/devzone/cda/epd/p/id/3257

The table should be taken more as a reference in terms of relationships between the different data types you can use.  The exact values will depend on the specific FPGA used, and I think this table was created for an FPGA other than the one on the IF-RIO.

For your second question, it depends on what you consider critical to your application.  If you are running short on FPGA resources, then this may be the best way to go.  But you will most likely need another filter after your interpolation, but this can be a much simpler filter that the Root Raised Cosine you are using for the first part.  If you have a lot of room on the FPGA, I don’t see any reason for not combining both filters into one and interpolating first.

One of our other modules, the NI 5441 uses two filters, a FIR filter first, and then a CIC filter second in the digital up converter in the OSP section.  The CIC filter is where most of the interpolation takes place and is not programmable.  It also has a traditional, but gradual, low pass filter roll off.  The first filter, the FIR, handles a smaller portion of the over all interpolation, but in addition, the filter used here (including the root raised cosine are designed (as much as physically possible) to compensate for the CIC’s roll off and create a relatively flat pass band.  (The FIR filters are created using the DFD toolkit.).

So, depending on what you want, the best technique is the one you decide is best.

Jerry