cannot set ADC_0_Port_A_Clk to 100 MHz

[pd2]

When I right click ADC_0_Port_A_Clk and click properties, a window comes up which lets me configure clock rates. The nominal frequency is set to 25 MHz, but the ADCs can run a 100 MHz. Is this a problem?

I set the nominal frequency to 100 MHz, but I get a message saying "Error: Nominal frequency 100.00 MHz is not within range 1.00 MHz to 25.00 MHz required for target."

When I compile my FPGA code, I get

Base clock: ADC_0_Port_A_Clk
Requested Rate: 25.001250MHz
Theoretical Maximum: 26.204077MHz

in the result. Since the Theoretical Maximum is only 26.2 MHz, does this mean I must use the DDC VI so the SCTL runs at 25 MHz or less?

[JerryAL]

Hi

The DDC in the ADCs cannot be bypassed.  So, the highest IQ Sample Rate you can use is 25 MSps.  You cannot get real data sampled at 100 MSps from the ADC on this module.  The timing to the FPGA will not be able to support this rate.

If you wish to use the ADC, you must configure the DDC with the ni5640R ADC Configure DDC.vi.  Depending on the Decimation you select, this will determine the IQ Sample Rate of the ADC IQ data.  If you check, you will see that the minimum decimation value is 4, so the calculation is 100 MSps (ADC rate) divided by 4 equals 25 MSps IQ sample rate.

Jerry

[pd2]

Thanks for that. I thought that passing 0 as the decimation rate would cause it to run at full speed. It's a good thing I found out about this.