LabVIEW FPGA SPI with NI 9651 dev board

[weejinky]

Hi Will,

I can make the control a type def but when I go to reconfigure the IO types I only get the choice of Write or Read never both at the same time. I think I must be missing a step. Is the driver going to be updated by NI?

Michael

[j_bou]

Hello weejinky,

Are you trying to configure I/O items to both read and write within the “Configure FPGA I/O Name Control Type” window? Each I/O item in this window can only be configured to either read or write. For example, if you created a CLIP and included DIO0 with bi-direction pin settings, you will then have 3 I/O items available in the “Configure FPGA I/O Name Control Type” window: bolean_1_in, bolean_1_out, boolean_1_enable. Each will have a corresponding read or write option.

The three elements above correspond to the same physical pin on the 9651 (DIO pins are tri-stated). In your FPGA code, you will have to use the boolean_1_enable to set the pin to either read or write. If  boolean_1_enable is true, then the pin acts as an output. if the boolean_1_enable is false, then the pin will act as an input.

Hopefully I correctly interpreted you question. Let me know if you have further questions.

j_bou

[weejinky]

Hi J_Bou

I am trying to setup the input cluster to the subvi IP Port (SPI).vi to work with the NI-SOM but because of the tri state nature of the SOM as you described I cant get what I create to match what the subvi is expecting. It looks like the subvi needs a cluster of FPGA I/Os that can be both read and write at the same time but I dont see how that is done with the SOM.

Michael

[weejinky]

Is there any update from NI as to if and when this driver is going to be updated?

[Spex]

Hi Michael,

The issue you are having with updating the IO cluster is the existing IP has filtering applied to the drop down boxes that require the IO nodes selected to have write, read, and set output enable methods available.  If you right click on each of the IO Name Controls in the cluster, you can set the properties to require Write-only or Read-only capabilities and allow you to select the SOM IO in the cluster.  You will have to intelligently decide if an IO Name control should be write (such as MOSI, CS, and CLK) or read (MISO).  

For the signals which are outputs, you will need to separately 'Enable' the output only IO Nodes in your application initialization.  Luckily, I think all the lines in SPI are unidirectional, so you don't need to re-architect the code to pass the 'Enable' node names into the IP.  

I'm also forwarding this thread to some folks who I know were working on optimizing SPI IP for the SOM.  Hopefully they will have an update and can post back to this thread.

Regards,

[RyanPoPo]

 Hey Michael,

We have been working on an API for SPI that should make things a lot simpler for users like yourself. It is currently in a Beta period, but we are looking to release the API sometime in the near future, and getting feedback from users is one of our primary goals currently.

I'll private message you a link to the latest build of the API. It has an example included for SOM as well, so that should help you get up and running quikcer. Just be aware that the API isn't released publily yet.

Regards,

Ryan

[roodrood]

Hi Ryan,

I have the SPI API working with my SOM with the onboard 40MHz clock. the SPI clock runs at 10MHz and is too slow for my application. I was wondering if I can do faster SPI communication with this API. I switched to a derived clock of 200MHz speed but the API complains about clock domain cross compatibility issues. seems like one of the memory blocks is not set to cross domain but when I try to configure it the cross domain option is disabled!

How do I fix this? 

Is it possible for me to get a copy of your new SPI API too. It would really help me with my project.

one more question: it seems like the DIO on the SOM can't deliver pulses faster than 100ns. but with the SPI API they give me faster pulses at 50ns! I tried to understand your code and it seems liek oyu guys use a single cycled time loop for this. My understanding is FPGA IO nodes can't be used inside a single cycle timed loop. How do you guys achieve this. in general if I have a fast derived clock how do I use it to output TTL on my DIOs with this new faster clock?

[RyanPoPo]

 Hey roodrood, 

I'll send you a link to the latest VI package via private message as well.

In regards to your I/O, you can use Digital I/O nodes in SCTLs on most targets, and definintely can on the SOM (it's how the SPI API functions). As for the memory items complaining about clock domains, can you provide more information about hwo your code is set up? Also, does it give you this error when compiling with slower derived clocks?

As for I/O speed, you can often drive the logic of a digital line at very fast rates, but the physical signal may not be able to keep up. For SOM, there have been some benchmarks done to determine the fastest frequency at which you can drive the DIO lines. There's more information at this link:

sbRIO-9651 Max DIO Speed?

I hope this helps.

Regards,

Ryan

[roodrood]

so here is my code and the compile error that i get for using a DIO node in a SCTL

[roodrood]

oh never mind, sorry. I forgot to take the WAIT VI out after I switched my while loop to a timed loop. It is compiling now. sorry