Create FIFO timing violation

[mr_Q]

Hello everyone! I am working with 802.11 application framework and try to save all samples in frequency domain from frame to further processing. For that purpose I create a long FIFO wich is 65537 elements depth in top level FPGA.gvi near other FIFOs such as TX to RF FIFO and etc. 

During the compiling phase a have an error caused by timing violation. LabView tolds me that in Create FIFO I have a Data Path Delay above 1.7 ns and I don't know how to fix it, because I implement FIFO in the same way as TX to RF FIFO which works well in current project. Does anyone knows the solution? Thanks for help! 

[Shalini.M]

Hi Mr_Q, 

Which target are you compiling to?

Could you attach a screenshot of the error and how you have the FIFO configured? 

Did you add in pipelining after creating this new FIFO?

[mr_Q]

Thank You for your reply! 

My target is USRP 2944R 

I added a feedback node as a Pipeline befor writing to the FIFO. It does not work. 

All screenshots are attached.  

[Shalini.M · Accepted solution]

Have you worked through all of the recommendations from the following help page on Resolving Timing Violations on the FPGA?  

[mr_Q]

Thank You for your help! 

I'd read this manual on Timing Violations but it did not help me at first. Anyway, I solved this problem!  LabView told me that time delay was in Create FIFO function, but the problem was that I cannot Write and Read from FIFO in single clock cycle. When I use pipelining between Write and Read functions, it start to work.