9074 hybrid mode

[jeffyy]

I want to use the 9074 in hybrid mode but can't get the data passed to the channels when going up to the chassis level. is there something i'm missing? i was able to do this on another cRIO model (9012). does the 9074 support this mode?

JY

[David_L]

This device supports hybrid mode.  What do you mean you "can't get the data passed to the channels when going up to the chassis level."?  Please provide some more details on what problems you are having so we can help you troubleshoot this.

[jeffyy]

What I mean is, I can move the C series module out of the FPGA target and place it under the Chassis target ( i asume this is then inhybrid  mode) but when i do that and drop a channel reference onto the block diagram, i get not data from the channel.

JY

[charris]

Jeffyy:

It sounds like you have the project set up correctly, but would you be willing to post up a screen shot of your project tree and your real-time VI? I'd like to get a better idea of the details; it sounds like there's a configuration setting we're missing somewhere.

Thanks!

[jeffyy]

Here is the rt hierarchy

[charris]

Jeffyy,

I was actually hoping to see the project tree itself, i.e. the expanded view of the project explorer window. I wasn't terribly clear about that, I'm sorry.

I'm specifically interested to see the modules/FPGA target arrangement on the cRIO, the block diagram of your real-time VI (where the FPGA communication occurs), and (if possible) your FPGA VI.

[Donovan_B · Accepted solution]

Hybrid mode requires that you have a compiled bitfile running on the FPGA to be able to read Scan Interface IO Variables.  Moving the module from the FPGA target to the RT target will enable the Scan Interface for that module, but the chassis will still be in LabVIEW FPGA Interface mode.

To get just scan mode access for the chassis, right-click the chassis in the project and choose Properties.  Then, change the Programming Mode to Scan Interface.  If you still want to use FPGA programming and the Scan Interface together (hybrid mode), you will need to compile a bitfile (empty if you don't want any programming on the FPGA yet or containing your FPGA code).  By compiling, the scan mode module support for the modules under your RT chassis will be compiled into your custom bitfile.  Then, on your RT VI, you will need to use Open FPGA VI Reference to your newly compiled VI.  Once this VI is deployed and running, you will get data from your IO Variables.

For more information, see this KnowledgeBase article as well as the CompactRIO Scan Interface Reference and Procedures.