LabVIEW FPGA Idea Exchange

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read clock rate from clock reference

In real time engineering usualy the clock rate is a parameter which is needed in calculations. Therefore it would be useful to be able to access that rate as integer (or float). It is clear, especially in fpga-programming that the clock (and its rate) is not a variable, that can be chosen by the application user. This idea is rather about code development in order to avoid bugs. In the current situation I am forced to define a seperate constant copying the clock rate; in the course of later code changes I risk to forget to change that constant, when changing the clock.

For the same reason it would be useful to be able to access a clock refernce of an fpga-vi (an with it its rate) form the calling vi.

Basically I want a VI like open FPGA VI ref which takes a RIO interface and returns a reference, except that it doesn't deploy a reference if one doesn't exist. It would instead pop out a boolean or error if you try to get a reference and there is no bitfile already deployed.

Two use cases I have in mind:

-Imagine if you need a cRIO to start working ASAP so you deploy your bitfile to flash and tell it to run on power-up. You still have to package the exact same bitfile with your RTEXE, even though its already deployed. This increases the size of your RTexe significantly. Lets say you version your RTexe and don't version the FPGA deployed to flash. Depending on what the signature check is, obtaining a reference to your bitfile may cause the "new" bitfile to be redeployed, eliminating the advantage of loading your bitfile onto flash in the first place.

-Imagine if you have a framework like veristand where you need to use a single bitfile in multiple locations which were written by different developers and possibly released at different times. The tools on NI labs (https://decibel.ni.com/content/docs/DOC-35574) help a lot and let you, once you have a reference, confirm the reference has all the interfaces you need to run your code. However, if you need to share references between code modules you must still be sure to obtain it in just one place and then share the reference yourself using a global or FGV.

Having the RIO driver solve this would be very helpful.

Better check for Compile Server

If you try to compile while pointed to a Compile Server that is for any reason inaccessible (server is down, firewall, typo in the hostname, etc.) you must wait through the generation of intermediate files, then you receive the error message that LabVIEW FPGA was unable to contact the Compile Server at your configured hostname/IP. Generating intermediate files can be a lengthy process and it shouldn't be necessary to wait through it just to find out if you have configured your Compile Server correctly. Any of the following would be a much better experience:

Attempt to connect to the Compile Server before generating intermediate files.
If the connection to the Compile Server fails after generating intermediate files, give the option of specifying a new Compile Server hostname/IP and retrying without having to re-generate the intermediate files.
At least put a connection check in Tools >> FPGA Module Options... so the user can test the connection to the Compile Server. You wouldn't do this all of the time, but if you run into a problem at least this way you can keep trying new configurations without generating intermediate files. Right now the best way to test new configurations is to create a blank FPGA VI (to decrease the length of generating intermediate files) and keep trying to compile it.

Run-Time Dynamic Dispatch Support

The LabVIEW FPGA module has supported static dispatch of LabVIEW Class types since 2009. This essentially means all class wires must be analyzable and statically determinable at compile-time to a single type of class. However, this class can be a derived class of the original wire type which means, for instance, invoking a dynamic dispatch method can be supported since the compiler knows exactly which function will always be called.

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpgaclassesinvis/

This is not sufficient for many applications. Implementations that require message passing or other more event oriented programming models tend to use enums and flattened bit vectors to pass different pieces of data around on the same wire. All of this packing and unpacking can automatically be handled by the compiler if we can use run-time dynamic dispatch to describe the application.

We call for the LabVIEW FPGA module to add support for true run-time dynamic dispatch to take care of this tedious, annoying, and down-right boring job of figuring out how to pack and unpack bits everywhere. Whose with me?

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FPGA compile automation tools

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Intermediate file generation in parallel

Improvements for Continuous Integration

Proper unit testing is a key component of large LVFPGA project success. As the number of modules grows, so does the number of units tests increase. We are working on automatic continuous integration methods that will continue to monitor the accuracy of all modules and assemblies throughout the project life cycle. IP Integration node and NI's wrapper around Xilinx IP makes this task more difficult. When our continuous integration machine refreshes the source code from the repository it has to regenerate these nodes in order to compile. The "Regenerate IP Integration Node Support Files..." tool does not always properly update all IP. It seems like the NI wrappers around Xilinx IP are most problematic. The only way a computer can properly update its version of the node is to open the VI and click through the Xilinx IP generation pages to get it to update.

As a rule we do not commit build products into our source code repository. One option would be to submit all the support files generated when first creating the IP integration node so that others users might not have to update. This can become messy and quickly unwielding. The problem arrises when changes to the IP integration node cause more or fewer support files to be generated. This then requires deleting some files from the repository and adding others which is tedious and leads to errors. One compromise would be if the IP integration created one single compact file that contains all the information needed (expect the input vhd, etc. files) that could be committed to the repository. Even better would be to roll this information into the VI itself. Neither of these might be ideal if the support file contents take up a lot of disk space.

Regardless there needs to be a better solution to allow for automated continuous integration testing.

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Please give us FXP-based enums

When instantiating case structures, the bit width of the selector has an influence on the efficiency of the code being produced. Of course various compiler optimisations will (may?) do a lot of this lifting for us if we actually wire in an FXP (which LabVIEW again tries to coerce to I32, but that's another battle) but I'd like to have the ability to create, use and convert to and from enums with variable bit-widths. Of course the only parameter of importance for this is the width of the FXP, the integer bits become essentially irrelevant.

I currently have to do a lot of U8 Enum FXP conversions in order to be able to force my case structures to adapt to a given width when supplying an enum to control some code. Readability would benefit greatly if the enum itself could "simply" be an FXT to begin with.

Boolean array to FXP

When parsing message packets in my FPGA code I'm often using a custom packing method with multiple individual datasets being packed into a single U64 (for example) for transport.

With the introduction of Malleable VIs, I would love to be able to create my own packing and unpacking Malleable VIs but don't yet see how. Problem is that the "Boolean array to Number" does not allow attaching a datatype like the "To FXP" does. I would like to marry these two functions into a "Boolean array to FXP" node where I can wire in my input datatype and have the output datatype automatically maintained in a malleable VI.

Remove restristions on FPGA target names

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Hi, since there an be a queue for compiling FPGA code, it seems natural to me to also be able to make a queue for generating intermediate files.

I'm working with 10 build specs. for compilation per project and generating intermediate files for my design takes aprox. 3-4 minutes. This means that I need to sit by my computer for half an hour just waiting and clicking build on every build specification. Sometimes I work with FPGA VI which need to build intermediate files for something like 7-10 minutes, so this is a pain.

It would be great if there was a way of just highlighting all build specifications for compilation with shift and just creating the intermediate files for them automatically one by one.

Can this be done?

Auto Increment

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I am currently running into this issue where I have some constant data I'm trying to write to some DO lines. I want this data to be a constant array on my block diagram, so I create the array programmatically under the "my computer" target. I then change the indicator that is populated to a constant and move it to the FPGA. When I right click and set the array to be a fixed size, it replaces all my data with 0's. I propose the data should not be cleared if I set my fixed array size to be equal to the size which the array already is.

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Build Selection option

Sometimes I just want to compile a lot of Bitfiles (Be it for a release or a debugging test case) and I have to right click each and every Build spec and choose "Build". then wait about 10 seconds and do the same again for the next build spec.

How about being able to select multiple build specs and then select "Build Selection" and have time to go for lunch while the PC queues up all the compilations?

I don't use a compile farm and everything is done locally but at least the queuing could be automated.

Shane.

I've searched but can't see anything similar - please add a method for setting the timeout for FPGA nodes. This includes the 'Open FPGA reference' and FPGA IO nodes.

If you disconnect a cRIO FPGA (e.g. NI 9148) from the network, it takes 20-30s for the IO node or Open FPGA reference to execute. This is really bad for the user experience as if they try to exit their application in this time it may take half a minute for the application to exit. It also means you may have to wait that length of time to realise that your FPGA has disconnected under most use cases (you can obviously have an external watchdog loop to check that the node is executing in a timely manner)

Please allow me to configure the timeouts for these nodes similar to the TCP/UDP or VISA nodes. They are very similar in how they operate to the FPGA nodes (i.e. a hardware device driver which is susceptible to disconnects!) so I don't understand why these have been omitted.

I wouldn't mind having to set the timeout as part of opening the FPGA reference and then internally have it use the same timeout for other IO nodes as follows:

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The first thing you hear about programming FPGAs with LabVIEW is: use single-cycle loops. But if you build a state machine (while-loop + enum + case structure), in many cases you cannot make the outer while loop in a single cycle-loop, because not every state fits into a single-cycle loop. Therefore you have to place the single cycle-loop into every case, which has to run in one cycle, which takes up block diagramm space and is cumbersome. Therefore my idea to create a single-cycle case structure: it uses the same compiling mechanism of the single-cycle loop on every case, which is capable of running inside a single cycle. It would be nice, if this behaviour is configurable, meaning I can decide from case to case, if it is a single-cycle case or not. Some kind of right-click menu options like these: "make this case single-cycle", "make every possible case single-cycle", etc. Of course the mode of the case (single-cycle or not) should somehow be displayed.

Regards,

Marc

LabVIEW FPGA Idea Exchange

read clock rate from clock reference

Get reference to currently deployed bitfile on FPGA target

Better check for Compile Server

Run-Time Dynamic Dispatch Support

FPGA compile automation tools

Intermediate file generation in parallel

Improvements for Continuous Integration

Fix tha latch point for FPGA property nodes

Please give us FXP-based enums

Boolean array to FXP

Size Xilinx IP icon to fit its terminal labels

Remove restristions on FPGA target names

Lets enqueue creating intermediate files

Auto Increment

Changing to a fixed size array shouldn't remove array data

Change Default Interface of FIFOs to Handshaking

Fixed Point numbers don't always show coercion dots.

Build Selection option

Add timeout input to FPGA nodes (Open FPGA reference, IO nodes)

Configurable single-cycle case structure