LabVIEW FPGA Idea Exchange

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This is the current situation when dealing with register creation on FPGA targets:

This is what I would like:

I am currently creating a group of classes to abstract out inter-loop communication and the ONLY thing changing between classes (aside from variations between Ragister vs FIFO vs Global and so on) is the datatype. Being able to link the Register creation to a data input (the data value of the class itself for example) would save a lot of work in such operations. If it were also possible to do the same for the Register stored within the class private data then implementing different classes int his way would be really easy.

Even without classes, the ability to autoadapt the type of registers / FIFOs in this way would be a real step towards re-usable code on FPGA.

Working with the NI 5785 our team had a hard time understanding how to use TClk without all of the extra (e.g. streaming) code that comes with the example.

Through support we were eventually put in touch with R&D and they told us how to initiate TClk by setting some of the FPGA controls. This was helpful but not intuitive.

TClk helps support beamforming applications shown in the NI Marketing but without this usability it is very difficult (impossible) to develop applications promised.

TClk also has other lower level features such as the delay correction. No info is posted on this either but it is a property we can read.

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For debugging, using FPGA VIs in interactive mode can be very valuable. I have, to this day, not been able to find out how LV determines if a bitfile and a VI match.

Therefore whenever I click on the run button for a VI, I'm never quite sure if the bitfile will match or not and often have to wait 1-5 minutes before I can resume working with LabVIEW. This is a very high price to pay for something which I end up cancelling. I would like very much if the IDE would TELL ME that the bitfile and VI don't match before starting a new compilation and thus wasting my time.

This is opposed to a CTRL_Click of the run arrow which explicitly tells the IDE to compile.

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I would like to access class attributes of my FPGA class hierarchy with property nodes. I prefer the property node API over VIs for data member access because it allows you to grab properties from across the hierarchy in a single node. This leads to a (much) cleaner block diagram and expedites development. For example in the screenshot below, the FXP attributes belong to the NI_9205 class, while the "_OP" attributes belong to the parent. I don't care about the Invoke node API over a subVI, because the wiring work and diagram appearance are about the same IMHO.

Thanks,

Steve K

Hide Trailing zeros from context menu

Show the price of sbRIO on the NI website

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Hello,

I have a LabView project which includes a Windows part and a FPGA part.

To simulate my windows part i use Conditional Disable Symbols in order to bypass the FPGA calls. ( Ex: DEBUG = TRUE/FALSE)

These project Conditional Disable Symbols are not used im my FPGA Vi's.

BUT, when i change the Conditional Disable Symbols values ... i have to rebuild my FPGA code ! This is not good !

The "Bitfile validity" check should be a little more intelligent.

The "bitfile update detection" should only take in account the Conditional Disable Symbols it uses.

Thank for reading.

Manu.

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VI scripting for FPGA programming

I didn't find something related to this, so I hope it's a new idea.

I use frequently VI scripting on LabVIEW, it is very useful for example to generate template VI's.

but this feature doesn't exist under FPGA, I mean some code is specific to this module, and I think it would be great to be able to generate FPGA VI's programmatically. For example in my job we make FPGA programming for Magnet Security. Even if global structure is the same for all magnets, we have to adapt a lot of things depending on type of magnet and instrumentation available. The idea would be to create ourself a kind of Magnet Safety Editor based on VI scripting specific for FPGA in order to allow non-programmers, but Magnet specialists, to generate themselves an adapted security system.

It's just an example, but when we see powerful of VI scripting for LabVIEW, it would give great results if it extends to FPGA, and even Real-Time module, why not?

Allow Parallel For Loops on FPGA

NI has released an exciting new product with the High-Speed Serial board which is essentially a Kintex 7 with GTX transeivers exposed.

https://www.ni.com/en-us/shop/model/pxie-6591.html

https://www.ni.com/en-us/shop/model/pxie-6592.html

Some applications we are working on would benefit greatly from having some way to expose the GTP / GTX / GTH transceivers ont he various NI FPGA boards to enable high speed serial transmissions on a wider product palette. Even the Virtex 5 supprts up to 16 GTP transceivers. Having even 8 of these available for Aurora communication would be a complete game changer as we could move over to optical links between individual devices.

In order to be able to make proper use of this, NI needs to offer GTX / GTH / GTP options for many of their boards. Imagine the power which could be unlocked by itnerfacing 8x Zynq 7010 boards with a single Kintex 7, each Zynq performing some aspect of pre-processing (Analog control, switching, some aspects of control) before sending results back to the Kintex 7..... For those of us working in Scientific areas, the prospects of a system like this is truly mouth-watering.

Single-Cycle Timed For Loop

When writing LabVIEW code for an FPGA target, the most important considerations are speed and resource usage. By using the single-cycle timed loop (SCTL), we can increase the speed of the program by allowing more than one operation to complete per clock cycle. We also decrease resource usage by removing the flip-flops that would be required to store values between clock cycles for the operations in the SCTL.

However, there are limitations of the SCTL. For some operations, it takes significantly less resources to implement something using a for loop rather than a single-cycle timed loop. With a for loop, one can auto-index a result at the border of the for loop (if the preallocation of arrays option is selected) to obtain a fixed-size array (valid on the FPGA). Below is the simplest possible example:

The equivalent with a single-cycle timed loop would be:

The replace array/subset VI consumes resources proportional to the size of the array. Depending on the operation being performed, this can increase resource usage such that it is more practical to use a for loop (as shown above).

I propose the creation of a single-cycle timed for loop. Here is a very rough mock-up (MS Paint is not the most adequate of image processing tools... you will get the idea):

This solves two problems: 1) It allows for the compiler to know how many times to loop will run at compile time. It also simplifies the UI by letting the user know how many times the loop will run without having to think through a condition. 2) It allows for the more efficient creation of fixed-size arrays through a SCTL (rather than through a for loop).

When I use a FPGA Read/Write control to set a state from Windows to the FPGA target, I would like to be able to search for all the places where that is done. If I do a search-Text for the FPGA Read/Write control variable names used to set the state, they are not found. The work-around suggestion from NI was "to include the text that you are looking for with each instance of the control, one way to accomplish this could be to label the wires going into or out of each terminal with the name of the control." This would work, but it would be better in a future LabVIEW version to have the search function be able to find the variable names.

Hello,

I recently have issue configuring FPGA Vis to be run seemlessy by the same host code, because of incompatible interface between VIs. Here is the Configure FPGA VI Reference Interface :

Configure FPGA VI Reference Interface

And here are two (differents) interface, fore FPGA 1.vi and FPGA 2.vi respectively, as seen in the context help. I just duplicate the VI for the example and get the tab order modified - see under Registers :

Context Help for FPVA 1.viContext Help for FPVA 2.vi

I think it could be more consistent to have the same kind of display in the configure dialog, with the same control order. It's quite confusing not seeing any difference when configuring a reference to discover that something is wrong at run-time (controls and indicators are separated, and then sorted alphabetically - I only set controls in my example code, no indicators). The context help over the dynamic reference finally helps me to figure out what was wrong but it tokk me a while...

Please note that the FPGA FIFOs have to be define if the same order from one bitfile to an other (if there is differents targets, or differents projects). This is correctly reflected by the configuration window.

So I suggest having a more coherent display of control and indicators interfaces, that correspond to the effective interface (just like the context help does), i.e. the tab order of the controls under Registers.

Best regards,

Smart compilation

Hi there,

I got following feedback from a LV FPGA user:

When developing a FPGA application in LabVIEW, after submiting a FPGA code compilation - usually quite a lengthy process - if you modify the code either on the Front Panel or Block Diagram while compiling is in progress, this results in a Compilation Error at the end.

And this occurs regardless the modification be only a mere cosmetic change, without any implication in the code that is being compiled.
This is quite frustrating when you realize that the compilation has failed (maybe after half an hour waiting) just because you unconsciously clicked and resized some control or node.

In such a situation, when LabVIEW detects a code change while the FPGA compilation is running, it should warn the user with a message box; if the user confirms the code change, the current compilation can be inmediately aborted or let it continue (at user option); on the other hand, if the user cancels the modification, nothing happens and the compilation continues to a successful (hopefully) end.

Thanks

Álvaro

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Make generated VHDL files accessible

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It would be nice if this code:

Case Structure version

could be replaced by this code:

Select version

but doing so gives an edit-time error specifying that "Select: Possiblity of Dynamic Refnum not supported for current target".

Is there a fundamental reason this can't be allowed? The behaviour is presumably the same in each case, and the references are from the same place in both cases. In the case structure, the exact same references that are passed to the Select node are used, with the same True/False choice.

It's not a huge issue, but it would be a nice usability/readability improvement.

LabVIEW FPGA Idea Exchange

Ability to define datatype of Registers / FIFOs from code (without needing the configuration dialog)

NI TClk and Ultrascale FlexRIO cards documentation

Interactive mode: ASK before starting a new compilation if source and bitfile don't match

NI Cloud Compile Farm: take advantage of cached cores

Allow access to multiple IO registers at once like on certain DIO modules

Support Property Nodes on FPGA Targets

Hide Trailing zeros from context menu

Show the price of sbRIO on the NI website

Conditional disable symbols should not systematically alter validity of FPGA bitfiles ...

VI scripting for FPGA programming

Allow Parallel For Loops on FPGA

"Update Firmware" button functionality is not described on NI documentation

Expose Serial transceivers for FPGA boards

Single-Cycle Timed For Loop

FPGA Read/Write Control name search

Reflect Interface Configuration in Configure FPGA VI Reference Interface

Smart compilation

Make generated VHDL files accessible

Support the LabVIEW Compile Farm Toolkit on Linux

Selecting between two I/O refnums not allowed