LabVIEW FPGA Idea Exchange

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RASTER SCAN

bonjour,

Voici l'erreur que j'obtiens quand je veux compiler mon programme FPGA

LabVIEW FPGA: La compilation a échoué à cause d'une erreur Xilinx.

Details:
ERROR:Pack:2310 - Too many comps of type "SLICE" found to fit this device.

Design Summary:
Number of errors: 1
Number of warnings: 89
Logic Utilization:
Number of Slice Flip Flops: 7,963 out of 10,240 77%
Number of 4 input LUTs: 10,607 out of 10,240 103% (OVERMAPPED)
Logic Distribution:
Number of occupied Slices: 5,523 out of 5,120 107% (OVERMAPPED)
Number of Slices containing only related logic: 4,143 out of 5,523 75%
Number of Slices containing unrelated logic: 1,380 out of 5,523 24%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 11,028 out of 10,240 107% (OVERMAPPED)
Number used as logic: 10,454
Number used as a route-thru: 421
Number used as 16x1 RAMs: 70
Number used as Shift registers: 83
Number of bonded IOBs: 90 out of 324 27%
IOB Flip Flops: 97
Number of MULT18X18s: 38 out of 40 95%
Number of BUFGMUXs: 2 out of 16 12%

Peak Memory Usage: 359 MB
Total REAL time to MAP completion: 19 secs
Total CPU time to MAP completion: 19

voici une capture ecran du programme

merci d'avance 🙂

FlexRIO Breakout Extender

This has been a huge frustration in my development. There is no way to debug a Flex RIO + NI1483 FPGA design other than to tweak, compile, and test with actual hardware. NI should provide a VHDL behavioral simuation of all of their modules so that full end-to-end simulation can be performed using advanced simulators such as ModelSim. This would facilitate a much more robust FPGA development cycle for their customers who have these types of tools available.

For the NI1483, a VHDL simulation combined with a VHDL Camera Link behavioral model would be even better. But the CameraLink model could be developed by the customers as it (At least) is a standard or can be gleened from camera manufacturer documentation.

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Hi,

I find Conditional Disable Symbols in FPGA code very useful especially in a R&D environment where needs and code change back and forth rapidly. However, I also find it hard to keep track of all these changes. I propose to add support for reading FPGA Conditional Disable Symbols from Host to enable VIs like "Is_FPGA_Function_A_Enabled.vi" that would allow for the Host program to know the state (hardware revision of sorts) of the FPGA bitfile and adapt.

I'll give an example to illustrate this proposal.

Function A is implemented in FPGA bitfile v1. Function B is implemented in Host and is based on multiple calls to Function A. Your boss now wants Function B implemented in FPGA for performance reasons with means to disable the code if required. For this you define a Conditional Disable Symbol in the FPGA project "FPGA_WITH_FUNC_B" and write FPGA code for FPGA bitfile v2. Switching between v1 and v2 is easy enough from the project manager, but for the Host side there's no way of knowing whether Function B is implemented directly in the FPGA or should be "emulated" via Function A as before. If you could do a check like "if FPGA_WITH_FUNC_B == TRUE" you could easily make the Host aware of this.

Regards,

solarsd

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Changing the encrypting algorithm of IP

fpga data analysis

Hello,

I've been thinking to an experiment in wich I would need to acquire single shot spectra at 1MHz, with a sinlge line camera (1024 pixels, 12 bit), and then manipulate this spectra performing this kind of operation:

[ (spectrum1 - spectrum2)/spectrum2 + (spectrum3 - spectrum4)/spectrum4 + ... + (spectrumN-1 - spectrumN)/spectrumN ] / N

As I don't have experience with FPGA, do you think it would be possible to do this kind of things considering that the data flow (1M*1024*12) will be something like 2GB/s?

Thank you,

Daniele

Similar to the overflow-status-functionality (which I missused in the picture below) it would be useful to make it possible to include handshaking bit(s) in the signal as well. It is true that this could be implemented using a cluster. However the additional cluster-level will imply a multiplication of type definitions; moreover a built in handshaking-bit-functionality could be included directly in the high-speed math functions an registers, so that a seperate 'output valid' terminal would not be necessary.

Custom UCF file location

When working with CLIP-generated clocks we need to have good UCF files for proper compilation control (Something we now have after WEEKS of debugging ).

At the moment the ucf files MUST be in Users\Public\Documents\National Instruments\FlexRIO\IOModules for the code to work even though all other CLIP-relevant files can be located anywhere.

Please let us use the ucf file located int he same directory as the CLIP we're using otherwise we'll end up with cross-linking nightmares between users who don't have the right version in their local folder.

Shane

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Add Description Field to FPGA I/O Properties.

The "FPGA I/O Properties" that can be set for an I/O point under an FPGA target consist of just the name for the I/O point.

On the other hand, the "Shared Variable Properties" that can be set for a similar I/O point under a cRIO chassis are much more extensive and include a description field.

I'd like to see a similar description field included/available for the FPGA I/O points. As it is information that is maintained as part of the "project", the reduced functionality normally associated with an FPGA should not be an issue.

As long as I'm wishing, it would also be nice to be able to export/import names/descriptions/properties from something akin to the "Multiple Variable Editor" for both "FPGA I/O Properties" and "Shared Variable Properties" and if an I/O module is moved from the FPGA level to the cRIO level or vice versa, allow us to transfer or import the relevant properties from one level to the other.

Default data type Single Precision (SGL)

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Dear All,

I am attempting to write some FPGA code, for a cRIO 9074, to act as a data logger for 50 sensors that I am fitting to a small lifeboat. I hope to save all the data to the 9802 SD card module. From my understanding, it should be possible to take the sensor input signals into the FPGA chip, compile them into an interleaved data group and then output them straight on to the SD card from the FPGA. This means there is no RT controller required; making the system more reliable and quicker. Is this correct? Or is my knowledge wrong?

I have tried to look for some example of this on the web but I am struggling to find any which do NOT use a RT control. Can anyone point me in the direction of some examples?

Few extra details: Sampling frequency = aiming for 10 KHz (will be reduce if system cannot handle it), Input modules include; 9236 strain gauges, 9234 accelerometers, 9205 analogue voltage inputs, anymore questions fire away.

Thanks in advance!

Pete

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Powering NI sbRIO device

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VHDL Labview & FPGA

DC to DC converter basics using Labview for VHDL to FPGA Control

I am fairly a novice, that is why simplifications required, before I begin thanks for them who will response in advance

I am designing a DC to DC (Intermediate Bus Converter, a step down BUCK converter, of 24 v input and output 9 v and 5 amp current), By using FPGA controller, having limited knowledge, I need to program this using VHDL, for which I take LabVIEW, but as I am new so do not have any idea as what are the steps that I need to take for implementation, what function that FPGA does in this so that it can generate 24 v and what other mechanisms that have to control inside or outside FPGA that it can give the desired output voltage, if you have any idea about this then I would be glad to receive the steps that are necessary to complete this

LabVIEW FPGA Idea Exchange

Organized Folders in LabVIEW Project for RMC Socket

RASTER SCAN

erreur lors de la compilation de l'FPGA

FlexRIO Breakout Extender

Provide VHDL behavioral models of NI standard Flex RIO interface modules

FPGA Forced Recompile on other Targets.

Additional Input Types for Method and Property Nodes

Access FPGA conditional disable symbols from Host VI

Make DRAM expandable, add USB add more I/O expansion options on sbRIO (and less expensive)

Changing the encrypting algorithm of IP

fpga data analysis

Option to include handshaking bit in signal (fpga)

Custom UCF file location

Drivers for the Atlys Spartan 6 board

Add Description Field to FPGA I/O Properties.

Default data type Single Precision (SGL)

Data logger with NO RT controller, using 9802 SD card module

Powering NI sbRIO device

Como configuro FPGA en el Compact- Rió?

VHDL Labview & FPGA