LabVIEW FPGA Idea Exchange

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Sometimes, you might not care about the outputs under certain input conditions. "Not caring" can lead to significant improvements in optimization and thus resource utilization but there's no way to tell LabVIEW right now that you "don't care". I propose we create new data types that can support "don't care". It should start with the booleans but when you convert a boolean array to an integer, if one of booleans has a "don't care" the numeric output also then becomes a "don't care" which is yet another data type we need as well.

Here's what a "don't care" might look like if the user didn't care about the output if the input was 2:

dont care.png

LabVIEW FPGA Host Interface

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Simulation Mode for CLIP

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This would vastly simplify making re-usable modular sub-vis to handle complex interactions involving reading and writing front-panel controls to communicate over the FPGA interface. Presently, this requires a lot of complex code to be copied onto an large complex top-level vi. Being able to pass registers linked to front panel controls would allow controls to be bundled into clusters of registers and sent to sub-vis that could then be generically usable for repeat functionality or across multiple "channels".

Simulation mode for CLIP

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Target non NI hardware

when you try to use serial NI 9870/71 with crio controllers it will lead you directly to access them from FPGA mode, however you will find it difficult or not allowed to use its connection with MODBUS device so it will need be accessed by scan mode by installing the specified software on your crio to enable scan mode for these devices , may be we need clear declaration in serial NI 9870/71 datasheet to show that its possible to connect them in scan mode as it guide us only to FPGA and what are the best practices to it

Unified Functions Palettes

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I have Labview 2020 installed, along with Vivado 2019.1.1_AR73110 (which is the version the vi package manager installed). My suspicion is there may be few bits missing from the Vivado installation that labview does, since said bits (like using a board definition as a starting point for a project) wouldn’t ever be necessary for the FPGA module’s normal operation.

The Short version is, Labview’s Vivado versions (2017.2 & 2019.1) behave the same way. I’d question why the C:\NIFPGA\programs\<VivadoVersion>\data\boards directory isn’t present (even if it provides no actual board definitions) in the labview installs if end users are allowed/expected to use the software for custom project uses (IE, FPGA IP export utility, expecting you to use the same vivado version), but ultimately the labview vivado versions do not appear to be missing anything major.

Maybe in future labview Vivado versions, include the data\boards directory, with a readme note about what to copy from a Xilinx Vivado version to get board presets to work, or leave the framework without any actual board definitions.

Hello,

Is there any possibility to use a dedicated file to change the Number of Synchronizing Register

Today we need to right click on the DIO + Propriety + Advanced Code Generation + Select Nb of register.

On a SBRIO 9607 I have to do it 96 times and if I change something with the CLIP generator I need to do it again.

In my design I use VHDL IP so the synchonisation is already done on the VHDL and I don't need extra clock.

I try to edit with Notepad++ the .lvproj file and change the NumberOfSyncRegistersForReadInProject or NumberOfSyncRegistersForOutputData but it's not clean...

If you have an idea it will save a lot of click.

Thanks

NI USB-78xxR use 325T FPGA

Scan Interface for R-Series Devices

The error cluster has a string to identify where the error occurred, "source". In a FPGA code the string is only accepted (no broken run arrow) inside an error cluster. I guess this is implemented in this way to maintain code compatibility when you move code to another kind of target. The problem is that doesn't matter what you write in these strings when you are in a FPGA environment, it's ignored.

Some people use the same error code to show a kind of error changing only the source to identify where. I got a software, written by somebody else, that used error code 5000 in all user defined errors, changing only the "source" string. That give me no clue where the error was happening.

Since in a FPGA target only the "code" is useful i a error cluster, I propose two solutions:

1) A warning when a string in a error cluster is not empty (compilation time);

2) The FPGA compiler converts the ASCII chars in "source" string of the error cluster in a fixed size array of bytes [U8]. This array will be converted into a string in a target that can handle it. This is very common when you read a error cluster indicator in a FPGA VI from a RT VI. This solution will have a little overhead but it maintains 100% compatibility.

I like the second solution a bit more. A limited number of characters should be allowed order to save memory. One solution to that is to have a configurable option to determine how many chars is the maximum allowed.

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VBAT Requirements of sbRIO-9651(SOM)

VBAT input voltage in VBAT Requirements of sbRIO-9651(SOM) should support less Voltage.

SPECIFICATIONS NI sbRIO-9651

http://www.ni.com/pdf/manuals/376962b.pdf

VBAT is for keeping the time on RTC.

Minimum of VBAT input voltage in specification is 2.875V.

In general, the button cell is used to keep time like a Mother board of PC.

For example, CR type Lithium button cell has Nomal voltage 3V and End-point voltage 2.0V.

In this case, if we follow the specification, we can not use this CR type lithium button cell . Many users would like to use this CR type button cell for RTC. So, if we can chang the specification of Minimum VBAT voltage from 2.875V to less 2.0V, it is easy to use in many cases.

Addtional "Interactive" FPGA mode

When debugging FPGA code, I still like creating debug code right there in the FPGA code with FP debug indicators. After some simulation I can then compile (the exact same code) and test with hardware.

The IDE, however, makes my life really hard. In the background, each VI has a default build spec or bitfile associated with it. When a tiny tiny change occurs in the source code (some of which seem overly sensitive BTW) the interactive mode will not start.

It would be nice if we had the option, assuming that the FP controls are identical, that we can start an interactive mode where the existing bitfile is used with the same FP of the VI source. A visual indicator that the bitfile MAY NOT be identical with the code would by a good idea. Sometimes changes are trivial, sometimes when fixing a bug, we might want to double-check old behaviour for a moment before starting a compile process. The ability to maintain the option to execute the last compiled code seems like it would be a nice addition.

And yes, we could make a RT app which interacts with the FP elements but since debugging code changes often (including FP elements), this is a problematic maintenance issue.

Floating point FXD

I find that I'm using large bit FXD to handle the dynamic range, but I only have 8 or 16 bit significant bits. I have an I2S input of 24bit numbers that I store in memory as U16 with the following incoding Number = A*2^(B), where A is a FXD(+/-11,9) and B is a FXD(+/-5,5). A and B are bit spliced array that form the U16. This allows me a 33% memory reduction covering a greater dynamic range by trading off resolution. Here the I2S input allows the counting of leading zeros or ones to create the number B and conversion back to 24bits is easy. Three items would make this a great help: 1. a typedef, 2. a quick forward convertor from standard form to FP FXD, and 3. gain inputs on math elements such as FFT if they canhandle FP values.

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Allow Analog IO nodes in SCTL

Hello,

I simulate small FPGA code parts from time to time, and use these while doing it.

There are 2 helpers.

1) Simulation time estimate and progress: Module_SimulationProgress_Caller + Module_SimulationProgress_Popup

Here the idea is to just add the caller VI and it will call and display progress.

It has some "autotune" funtion to not call popup to often, but still update once in a while. It tries to hit around 0.5-1.5 sec in update.

This will minimize time spend on popup after some iterations. It also makes it possible to stop the main sim VI.

The estimator only works if your code is fairly static.

2) Data collector while running: Module_FGV_DataCapture.vi

Here the idea is to collect data (in fast buffer) while simulating and use it to display while simulating.

It has 5 buffers that can have different number of elements in them, but all have same length.

Then in a "slow" loop I update graphs once every second, then i can abort if i see something wrong.

This is to avoid having graph plotting in highspeed loop or using graph after simulation is run.

3?) Maybe i will add a plot VI that can take data in from the buffer, just to clean up simulation VI, and make it generic.

Can i get some feedback if it is good or not? Any other sugestions are wellcome!

Or how you do your small FPGA simulations?

Thanks.

LabVIEW FPGA Idea Exchange

New data types that allows for "Don't Care"

LabVIEW FPGA Host Interface

Simulation Mode for CLIP

Provide a means to link a front panel control on the top-level FPGA vi to a register

Simulation mode for CLIP

Target non NI hardware

NI 9870/9871 should be used in scan mode while connecting devices with MODBUS

Unified Functions Palettes

Another way to import the board support configuration

RMC Socket Number of Synchronizing Register

NI USB-78xxR use 325T FPGA

Scan Interface for R-Series Devices

The text in the "source" component in a error cluster is useless in a FPGA VI

VBAT Requirements of sbRIO-9651(SOM)

Addtional "Interactive" FPGA mode

Display max clock rate that can be achieved during development itself

Floating point FXD

Labview FPGA CLIP node support for single precision

Allow Analog IO nodes in SCTL

Easy and small FPGA Simulation helpers