LabVIEW FPGA Idea Exchange

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Currently Measurement & Automation Explorer (MAX) only shows the following information for a typical R-Series card:

 

MAX-R-Series.png

 

It would be helpful to add a "Device Pinouts" tab that shows you all the pin assignments for your Analog and Digital IO:

 

MAX-R-Series-Device-Pinouts.png

 

When working with alot of fixed point math (think FPGA development), unless you are content to simply let LabVIEW decide what precision you want in your fixed point data types, it is extremely cumbersome to (right click->properties->Output Configuraton->Uncheck Adapt to source......, close window, move to next function and repeat and repeat and repeat. This is especially true if you end up needing to highly optimize your code.

 

It would be nice to have something like a floating window that could be opened that would display the output configuration data for the selected function or control and allow editing without the need for multiple mouse clicks. The window would automatically update with the configuration of whatever function or control was currently selected.

 

fixed point config.PNG

I'm currently looking for a way to read out the FPGA version number from the FPGA.

All I found was a way to parse the *.lvbitx, but that's not what I want.

Are there any plans to store the version number in a FPGA register to be read out at runtime?

 

Best regards

Thomas

Old Title: FPGA Case Structure Needs To Display Enum Values

 

In LabVIEW the case structure can show enum values, while the FPGA case only shows the numeric value. Would like to see the below example capable in FPGA.

Untitled.png

Writeable inputs to FPGA I/O nodes can be left disconnected without any warning (or broken VI indication) from the VI in which the I/O node is used. This can cause some vigorous head-scratching if the missing connection is not immediately obvious as in the screen shot below. For obvious reasons, FPGA controls have no connector assignment or "Recommended, Required, Optional" attribute. In that case, and to avoid playing "Where's Waldo" on the block diagram, I suggest making FPGA I/O node input connections implictly "required", and if not, the VI would be broken. This would be the same behaviour as seen with cluster nodes. 

FPGANode.png

This might have already been asked, but I couldn't find any posts.

 

X-Nodes are huge in comparison to the size of a subvi or most anything else on the block diagram of code, so lets shrink them down.

 

Can we remove the Read/Write box?  We already have the little triangle to tell us the function/direction.

Can we use the node name instead of the generic term Data/Element?  It's already there.

 

From there we can model it after a property node using references instead of error lines or we can model it after the IO node which is a little cramped but gets the job done.  Both options retain a purple/pink bar to help identify it's X-node-iness.

 

X-nodeShrink.png

When there are many controls on the front panel of the FPGA, selecting the control from a Read/Write Control node in the host can become a pain.  It is one very large list of controls on the front panel of the FPGA.  This list has no scrollbar, no browse, or search feature, and no obvious way of grouping controls.

 

Here is one example of a front panel, and a video showing how long it takes to scroll through the list of contorls.

 

FPGA Front Panel.png

 

And here is the video of me scrolling through the controls:  http://screencast.com/t/PLzptTwq58aw

 

There is plenty of room for improvement.  Here are just a few ways I think NI could make this better.

 

Browse and Search

 

When using a Property Node, or Invoke Node, the very top option is to "Browse..."  From here a list of all properties, or methods can be seen in a resizeable window.  Here you can also search, and sort alphabetically.  The Read/Write Control node could have similar functionality making selection of controls easier.

 

Front Panel Selection From FPGA

 

There could be an option for creating a node by selecting the controls on the front panel of the FPGA.  A solution that may work today, is to select the controls, then invoke a custom QuickDrop command that creates the node and puts it in the clipboard so it can be pasted in the host VI.  If this were to become an option, I'd hope there is a way to combine two nodes into one, by concatenating the controls of one onto the other. 

 

Front Panel Selection From Host

 

Lets say you already have the Read/Write Control node on the host.  There could be an option by right clicking that would open a new window, showing a static image of the front panel of the FPGA, which the user could then click on.  This would be great because the developer probably already knows the control they want based on the front panel location.  I don't know how possible this is because you could load a bit file which won't have any front panel information. 

 

Easier Grouping of Controls

 

Right now there is a way to group controls of an FPGA.  This feature is never talked about, and doesn't work on dynamic bit files.  Here is a discussion where I describe the steps to make controls grouped on the host.  Still this isn't supported on all FPGA setups, and you have to conform to a specific naming convention.  Why can't controls that are grouped on the front panel, just be grouped in the host?

 

 

This idea exchange is really for any kind of improvement to the FPGA control selection.

Now that most numeric operators have the ability to saturate it would be nice to be able to differentiate these operations.  I know that the majority of the time you can determine this information easily with the context help but this would make it much easier to spot.  I tend to copy operators that are already being used in my vis than to grab a new one off the pallet.  This would let me know which type of operator I'm copying.

 

18007i82E22C521A6F662A

The error "You must recompile the VI for the selected target" appears for reasons that, to me, are often obscure or even inexplicable. Recompiling is, as we know, painful. It would be good if the error message included the reason(s) for refusing the existing bitfile, since then I may be able to work out how to stop it happening.

I understand the message comes because LabVIEW decides there are "dirty dots" associated with the bitfile, what I would like the error message to tell me is which dots are dirty and why.

The latest Virtex-7 FPGAs have something like 20 times the computing power of the biggest FPGA supported by LabVIEW FPGA; it would be cool to be able to get those on a FlexRIO card.

 

Other companies make FPGA boards with up to 32 GB of RAM, the biggest FlexRIO has 512 MB; would be cool to have FlexRIO cards with RAM in the gigabytes.

Vision is available under LabVIEW 64 bit and this makes sense since vision can generate very large amounts of data.  I think now is the time to bring FPGA over to LabVIEW 64 bit as well.  With FPGA systems you can also generate very large data sets.  Also with cards like the PCIE 1473R, you have a VISION requiring card that generates lots of data, but it requires FPGA, so you can only use it in LabVIEW 32 bit.  This is not a good thing.  It has been 5 years since LabVIEW 64 bit has been released  it is time to finish moving the addons over to 64 bit.

We can programmatically mass compile VI's and build executables but there is no easy method to compiling FPGA code.  We have a large application that consists of C++ and LabVIEW code.  We have automated our build process but we still have to compile the FPGA code using a procedure.  It would be nice to write a script or a VI that would compile all of our FGPA code.

The Control / Indicator pull down menu gets unwieldy with a lot of Controls on the FPGA Front Panel. 

 

I would like to be able to sort the names alphabetically so they are easier to pick in the pull down list.

The FPGA compilation results should be copied to a file in the folder with the bitfile.  This is needed to track the history of compilation results, especially useful when using source code control.  Right now they get overwritten with each recompile.

 

Adding a Post-build action VI to the FPGA build spec, would also enable something like this.

On PC and RT targets, when you right click on a specific property in a property node, you can directly open the help for that property:

 

normal property node.png

 

 

However, on an FPGA target, you can't open the Help for a specific property or method by right clicking:

 

fpganode.png

 

What happens if you click on 'Help'? It takes you to a page that explains the purpose of a property node. Rarely if ever is that what I actually want. Instead, I want to know about 'Linearization Coefficient 1.' My only option is to open up the Help and search for that specific property, which may or may not be easy to find.

 

My suggestion is to add a direct link to the help for every FPGA property and method in the right click menu.

LabVIEW FPGA gives users the ability to prototype FPGA code before they even have the hardware. This is incredibly useful. However, this requires you to manually add your controller, chassis, fpga, and C series modules. The process of adding C Series modules could be improved. Currently, you only have the option to add one module at a time. This isn't too difficult if you only have a few modules. However, if you have a full chassis of modules and a few ethercat expansion chassis, this process can be extremely time consuming. It would be nice if you could add multiple modules at the same time like you can with compactDAQ.

 

 

Current

 

Current method of adding C Series Modules. It takes a long time to add each module individually.

 

 

Proposed

 

Current method of adding cdaq modules. You can add all of your modules from one screen.

Fixed point constants like to show you a lot of precision more often than not.  It would be nice to be able to right-click a number and instantly select hide trailing zeros.

17843iF72A0566F8914140

I love using enums because they can often make discrete options much clearer. Example:

enum clarity.PNG

But, at least as of 2017, the below code is going to use fewer resources and propagate faster because LabVIEW is going to use an 8 bit register above instead of the two bits below. 

 

My solution is to allow smaller integer representations of enums (I'd use a U2 in the above case).

 

Ideally the user wouldn't even have to specify the integer size, it could just calculate the minimum at edit time and show the user what it is.

Hello,

 

I have a LabView project which includes a Windows part and a FPGA part.

 

To simulate my windows part i use Conditional Disable Symbols in order to bypass the FPGA calls. ( Ex: DEBUG = TRUE/FALSE)

 

These project Conditional Disable Symbols are not used im my FPGA Vi's. 

 

BUT, when i change the Conditional Disable Symbols values ... i have to rebuild my FPGA code ! Smiley Mad This is not good !

 

The "Bitfile validity" check should be a little more intelligent.

The "bitfile update detection" should only take in account the Conditional Disable Symbols it uses.

 

Thank for reading.

 

Manu.

Number to Boolean Array and Boolean Array to Number along with array manipulation functions (index, replace, reverse) are commonly used methods in FPGA for doing bit manipulation on arrays of integers inside SCTLs. Not having access to these functions is prohibitive and results in having to write code like this:

image.png

This becomes very unwieldy when dealing with arrays of 20+ elements. If Number to Boolean Array and Boolean Array to Number are truly no-op elements, then they (along with basic array manipulation nodes) should be added to the list of supported nodes inside for loops inside SCTLs.