LabVIEW FPGA Idea Exchange

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Memory Initialization VI Input

Memory initialization is one of the more tedious aspects of LVFPGA coding. A lot of my LVFPGA vis have multiple memory elements that I need to access simultaneously for a given operation. I've tried to streamline the initialization process by making all memory initialization vis read from an init values file and populate the array indicator. However now I have to have multiple initialization vis reading from different points in the same init values file. If I could somehow get a parameter into the memory initialization vi, I could programmatically select from where in the init values file to read. Here is how this could work:

Save FIFOs in a library

DSP48E2 Implementation

FPGA compile automation tools

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Hello,

Recently, Last year, i've had a bad experience, when i tried to compile my old FPGA applications with Windows 10.

=> The FPGA ISE XILINX compiler is no more compatible with Windows 10.

Will something be done ? I got no clear answer from NI support ...It should be a XILINX problem !

The issue is that some products on the NI web site, are sold without clear information about the incompatibility with Win 10 !

Please, add a "clear highlighted Warning" on the product page in order to inform about the problem : On FPGA boards and on CRIO targets ...

Thanks for help.

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Xilinx supports BRAM primitives (FIFO and normal BRAM) with certain varying width read and write ports. For some applications, the ability to write 2x 16 bit values to a FIFO in one loop and read 1x 16 bit value from the FIFO at double clock rate in another loop can be very useful.

As it stands, the IPCore for such BRAM primitives, although present in LabVIEW FPGA, cannot be used without a CLIP (essentially making this aspect of the IPCore useless).

It would be cool if LV would expose the ability to have differing read and write port widths for BRAM.

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DMA Channel instantiation

I don't like static resource definitions FIFOs, Block RAMs or DMAs in my projects. I prefer to have the code declare such entities as they are required because this makes scalability much easier to achieve.

For FIFOs, BlockRAM and so this is no problem, but there are two things we currently cannot instantiate in code:

DMA Channels

Derived clocks

To deal with the first, why can't we define a DMA channel in the code? When parsing the code before compiling, the presence of a DMA channel can be autodetected and added to the interface for the Bitfile.

To try to decouple my code from static DMAs, I actually have started defining my core FPGA VIs as accepting FIFOs with Write functions (For DMAs to host) or Read functions (for writing to FPGA) required. I can then, without having to change my project, wrap this FPGA VI in another VI which can then input wither a DMA channel (which unfortunately must be defined in the project) or a standard FIFO which cen then be used for debugging.

Please allow for the instantiation of DMA channels in code.

Relative Paths for Xilinx IP

When using the Xilinx IP nodes in LabVIEW FPGA it becomes very difficult to support source code control and branching. The biggest issue is the fact that the "Folder for Support Files" entry is absolute. So when we need to branch the code to isolate new feature development from the main trunk the relative path is now wrong. Please make this and all other paths relative to support a more robust development environment.

The CORDIC High throughput functions available in LabVIEW are capable of running at high frequencies, thus allowing FPGA code to (for example) multiplex multiple demodulators without exploding device utilisation.

Unfortunately, the option to apply a Gain correction to the results does not pipeline the actual multiplication, thus artificially limiting the available speed of the CORDIC algorithms.

In my code I always deactivate the Gain compensation and do this "manually" allowing the code to compile at much higher frequencies and more efficiently utilising the FPGA device.

It would be great if it were possible to also pipeline this multiplication as part of the CORDIC High-throughput node instead of being forced to implement the multiplication separately.

LabVIEW FPGA Idea Exchange

Check for Invalid Use of Global Variables in LabVIEW and Alert User Before Compiling

Don't recompile if a memory or IO added for a different VI

Memory Initialization Browse Button Default

Memory Initialization VI Input

Configure Memory / FIFOs from Outside FPGA Target Scope

Save FIFOs in a library

DSP48E2 Implementation

"Update Firmware" button functionality is not described on NI documentation

FPGA compile automation tools

Change Default Interface of FIFOs to Handshaking

Colour coding for Estimated and Final timings

LabVIEW FPGA ... limited only by Windows 10 !!!

BRAM Primitives with different Read / Write data widths

Remove Stacked Sequence Structure from the FPGA palette

Make FPGA Registers searchable and Quick dropable

DMA Channel instantiation

Handle Fixed Point Integers Going Into Case Structures

Relative Paths for Xilinx IP

Extend Butterworth filter to allow multi-channel 32bit filters

Pipelining gain compensation in CORDIC algorithms