Acquire RVDT

[GerdW]

Hi Ayous,

even though your message is (temporarily) moved into quarantine I will answer your question:

• The NI9263 is spec'd as ±10V with ±1mA output current MAX
• Your RVDT is spec'd with a primary input resistance of 20…150 Ohm. This will result in a current of 10V(peak)/20Ohm = 500mA max. (I hope I read the text in the image of your French datasheet correctly.)
  

I repeat my previous message: read the datasheets!

(And apply basic knowledge for electrical circuits, like Ohm's law and Kirchhoff's rules.)

[Ayous]

GerdW,

So, I really don't understand the link between the maximal current of the card and maximal current of the RVDT. In my case, do I need 10V/150Ohm = 66mA minimum to supply my RVDT ? It seems big,

Respectfully,

[GerdW]

Hi Ayous,

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@Ayous wrote:

In my case, do I need 10V/150Ohm = 66mA minimum to supply my RVDT ?

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You need atleast 66mA as those 150Ohm is the upper limit of the input resistance!

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@Ayous wrote:

It seems big,

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No, this is a usual/typical value for such type of sensors…

Again: apply simple electrical equations (like R=U/I) to the values provided in the datasheets!

Your NI9263 is an AO module used to provide industrial signals (±10V), it's NOT a power supply to drive devices with higher power consumption…

[Ayous]

Hi GerdW,

I used your answers to find a solution and I found it.

By using my module's excitation and by recording the VS1, VS2 and excitation signal with 3 different AI of my NI9215, I'm able to compute the phase shift by myself and the re-linearize the sawtooths.

I have a little last question, you said earlier that you do the computation by you own when you acquire RVDT signals, is it possible to do it through FPGA ? Because I'm actually using some VI only disponible through the RT to compute it (RMS computation, peak detector for the phase shift..)

Respectfully;

[Henrik_Volkers]

If you create the exitation with the FPGA , you can sample in phase and you just have to choose the rigth samples for simple decoding.

No need to find peaks. 

However, since you have a FPGA you can implement the PLL demodulation proposed in the link of my previous post.