Analog In FPGA Rio

[tomnz]

I have a cRIo 9114 chassis and a cRio-9022

I am currently getting to know it. I have never programed real time LabView before, only ordinary LabView so I am doing simple tests.

I have tried in scan mode and my analof input works fine (NI 9234). I am now trying an FPGA example (I assumed that scan used the processor and not the FPGA?).

I have a program which I compiled on teh FPGA which is just a sequence with a timer (see attached). I then compile it and it compiles fine.

I then set up a host vi and use a reference (see attached). I run it and teh light flashes on the FPGA as if it is running but nothing is shown on the chart (unlike in scan mode). What am I doing wrong? I also attach my project listing,

Thanks

Tom

[nathand]

The FPGA code needs to be in a loop, otherwise it only runs once.

EDIT: take advantage of the FPGA simulation tools by right-clicking on the FPGA target in the project explorer and setting it to run on the development PC.  It won't run as fast as on the FPGA but you'll be able to use the standard LabVIEW tools to see what is happening in your VI.

[preston_johnson]

With Dynamic Measurements (sampling higher than 200 or so Herz) you really want to use DMA high speed transfers and NOT the scan engine.  With high sample rate 24 bit C series modules, the Scan Engine is really a poor choice. 

Consider using one of these reference designs, it will get you up and running and very quickly

https://forums.ni.com/t5/Example-Code/Reference-Application-for-NI-CompactRIO-Waveform-Acquisition/t...

and this one build on it

https://forums.ni.com/t5/Example-Code/Embedded-High-Speed-Data-Logger-Reference-Design/ta-p/3996474

[tomnz]

Many thanks for that. I put the loop around it and running on the PC as a simulator it worked. However, it doesn't work on the FPGA device though it does compile

with no errors. Why would this be?

Also, how do you stop it (on the FPGA)? I have a boolean stop on the while loop - does this stop it? It stops the VI ok but I am unsure whether it still runs on the Rio.

I tried a shared variable to stop both loops at teh same time but it would not accept this.

Thanks

Tom

[nathand]

Depends a bit on what you mean by "doesn't work" on the FPGA.  Do you get any errors out of the FPGA nodes in the host VI?  That would be the first thing to check.  Also make sure that when you open the FPGA VI, you have it set to run automatically (or that you add an FPGA method to start the VI separately).  Shared variables are among the many items that you cannot use on FPGA.  You can, however, put a boolean control on the FPGA front panel and use front-panel communication from the host to set that boolean true.  I'm pretty sure closing the FPGA reference will stop the FPGA VI, and there is also an FPGA Abort method.

[tomnz]

My Target software now look like this - not sure if this is how you do it.

I have since found out that it does read in values in simulated run  form but they are rubbish values.I am feeding in a sine-wave.

Tom

[nathand]

That's the right idea, although I'm not sure about the effect of using a timed loop when you have a timing mechanism inside the loop.  Check your analog input configuration within the project.  Also check the units of the wait time, on FPGA it may be clock ticks where you're expecting milliseconds (not that this should affect your readings).

I don't understand what you are saying about "it does read values in simulated run."  If you're running in simulation (executing on the development PC) with simulated IO, you'll get random data regardless of what you are feeding to the real input.

[tomnz]

Aha! Sorry I thought it was still reading data but much slower - so it just generates random data! Got it. So in that case it isn't reading anything at present when run in the target for some reason. Yes I checked the timing units - using microsecs. I will look at it again then.

[nathand]

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@tomnz wrote:

Aha! Sorry I thought it was still reading data but much slower - so it just generates random data! Got it. So in that case it isn't reading anything at present when run in the target for some reason.

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Depends on which setting you choose, and what your device supports.  Some FPGA devices do support simulation with real IO, so if your device supports it and you chose that option, it should read real data, just slowly.  But in this case it sounds like you were running with simulated IO.

[tomnz]

I have no idea what it suppporst at present, but when I run on the FPGA the output sits at zero. I'll try reducing the sample rate.