Attempted to access DRAM Address 524288

[MrQuestion]

When running my LabVIEW FPGA program in ModelSim 6.5c using the FlexRIO PXI-7952R external memory I get the following fatal error in my ModelSim Transcript Window

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# ** Note: Running
#    Time: 2412750 ps  Iteration: 1  Instance: /tb_nifpgasimulationmodel/mainstimulusblock
# ** Note: SendSettings
#    Time: 4863 ns  Iteration: 1  Instance: /tb_nifpgasimulationmodel/mainstimulusblock
# ** Note: Running
#    Time: 7741500 ps  Iteration: 1  Instance: /tb_nifpgasimulationmodel/mainstimulusblock
# ** Note: StartDMA_NOW
#    Time: 7741500 ps  Iteration: 1  Instance: /tb_nifpgasimulationmodel/mainstimulusblock
# ** Note: Running
#    Time: 11011500 ps  Iteration: 1  Instance: /tb_nifpgasimulationmodel/mainstimulusblock
# ** Error:
# ===================================================
# Error occurred
#
# Possible reason(s):  
#
# LabVIEW FPGA:  An error in the LabVIEW FPGA Module has occurred.  
#
# Attempted to access DRAM Address 524288
# For simulation, the valid DRAM address range is 0 to 524287
# Limiting the address in one of the following ways might correct the problem:
#
# Socketed Clip - Random Access: Only access addresses within the valid range.
# Socketed Clip - FIFO: Limit the total number of elements written to the FIFO to the maximum range.
# FPGA Memory Items: Only access addresses within the valid range and avoid accessing memories allocated to partitions beyond the maximum range.
# ===================================================
#    Time: 11930 ns  Iteration: 1  Instance: /tb_nifpgasimulationmodel/nifpgasimulationmodel_instance/lvfpgasim795xtop_instance/lvfpgasim795xdrammainx/genbank0mig/drambank0controller
# ** Error:
# ===================================================
# Error occurred
#
# Possible reason(s):  
#
# LabVIEW FPGA:  An error in the LabVIEW FPGA Module has occurred.  
#
# Attempted to access DRAM Address 524288
# For simulation, the valid DRAM address range is 0 to 524287
# Limiting the address in one of the following ways might correct the problem:
#
# Socketed Clip - Random Access: Only access addresses within the valid range.
# Socketed Clip - FIFO: Limit the total number of elements written to the FIFO to the maximum range.
# FPGA Memory Items: Only access addresses within the valid range and avoid accessing memories allocated to partitions beyond the maximum range.
# ===================================================
#    Time: 11932500 ps  Iteration: 1  Instance: /tb_nifpgasimulationmodel/nifpgasimulationmodel_instance/lvfpgasim795xtop_instance/lvfpgasim795xdrammainx/genbank0mig/drambank0controller
# ** Fatal: (vsim-3421) Value 524289 is out of range 0 to 524287.
#    Time: 11932500 ps  Iteration: 1  Process: /tb_nifpgasimulationmodel/nifpgasimulationmodel_instance/lvfpgasim795xtop_instance/lvfpgasim795xdrammainx/genbank0mig/drambank0controller File: nofile
# Fatal error at a source-protected location
#
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In the first couple of lines you can see the notes that my testbench is outputting.

When I start DMA FIFO process at "STARTDMA_NOW" The fifo starts to buffer, and then my algorithm starts to fill the DDR RAM. This does appear to be related to an addressing issue. My released project will need several different memory blocks megabytes in size. But for my test bench I'm only asking for a couple hundred bytes.

I am using the default external DRAM memory manager in the LabVIEW project, and the project has all memory elements shared equally in the Granted Time round robin resource manager in the LabVIEW project.

I have managed to minimize my DRAM elements to the smallest size that LabVIEW will let me. By doing this I can now write to at least two memory elements before the ModelSim Error.

It appears that LabVIEW is just tossing the memory elements anywhere it wants to in the memory map and it is exceeding ModelSim's capability to accurately simulate it.

Since the memory elements as small as they will go (it says actual number of elements 131072), this will never go smaller; I seem to be stuck.

I need to get LabVIEW to adjust the memory map so that ModelSim can read it, or I need to adjust ModelSim to read outside the 524287 address range.

(and in case somebody asks, I am not address outside this range. I only have a few elements. I am assuming the address that I'm looking at is only a pointer in addition to the start of my allocated memory block that Is created for me.)

Regards,

[MrQuestion]

When searching for issues related to (vsim-3421) I found the following on the Xilinx Website.

I am using Xilinx Tools 12.4 in LabVIEW 2011. Could this issue be related?

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http://www.xilinx.com/support/answers/40051.htm

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[Kevin_H.]

So this one could be a little tricky to figure out. I haven't found any support documents on DRAM and ModelSim which suggest any answers to your question. Could you send me a zip file with your project and all associated files/dependencies (minimized and compiled if possible) so I can try to reproduce the problem on my end? Are you using VHDL Test Bench or LabVIEW Test Bench? Could you send me the Test Bench as well?

Regards,

Kevin Horecka

[MrQuestion]

I've created a new project for this post that demonstrates this problem.

The attached project has 4 DDR memory elements. It appears that LabVIEW can only partition the DRAM in 2^17 blocks. I think this is important to note because if ModelSim can only address up to 2^19 elements (524287 elements). So if labview is fixed at 2^17 elements per partition then the max number of memory partitions you could ever access would be 4. This is regardless of how much data you really want.

But there appears to be more to this story. In this example ModelSim kicks out a fatal error when I try to read from the third partition. This indicates that LabVIEW has additional memory partitions sitting on the DRAM, or it just picks some place to start the partition instead of starting at location zero in the memory map. (speaking of which LabVIEW FPGA really needs to get a memory mapping tool so that you can see what is really going on)

 in my top level VI "tmp-ramtest2.vi" All that I'm doing is writing to three memory elements and then reading them back.

In my debugging I have added time delays between each step and added front panel elements so that it is easier to see in the ModelSim Simulation

As for my ModelSim Test Bench I just used the default LabVIEW generated testbench with the line "wait for 4 ms;" added before the NiFpga_close procedure. This gives the simulation time to run the VI.

Please note I'm not looking at optimization at this time. I'm aware that the DRAM can be optimized in batch read/write modes.

Right now I'm just trying to simulate writing and reading from three partitions.

Any Ideas or suggestions would be much appreciated.

-Theo

[Kevin_H.]

I'm working on getting ModelSim 6.5c installed, but I'm going to have to find an appropriate license. Let me know if you find anything else along the way, and please feel free to post back for updates! I'll be doing more troubleshooting tomorrow.

[MrQuestion]

The same warning comes up when you use the ISIM simulator that you can install with LabVIEW FPGA 2012. It is probably using the same VHDL component to simulate the external RAM.

[Kevin_H.]

I've managed to get the right version of ModelSim running and I'm getting the simulation library set up. Probably won't have any results for you until Monday though. Sorry about the delay!

[Sev_K]

Hi Theo,

Could you attach an archive of your "D:\ro_apps\simulation\DDR_Test\FPGA_Target\tmpramtest2~16" folder. Also, did you make any changes to the "tb_NiFpgaSimulationModel.vhd" in the user folder?

[MrQuestion]

Attached is my testbench. As described this is mostly the default test bench that LabVIEW creates with the exception of line 255 where I added a "wait for 4ms;" So that the test bench would run long enough to see the error.

There are several other engineers that are also facing limitations in their designs because we can not simulate this. Usually in our test bench we are only interested in a couple key state transitions and data points.

I greatly appreciate any help that you are anybody else can provide.

[Sev_K]

Hi Theo,

I wasn't able to replicate the error that you are getting in ModelSim and I was running into a few other fatal error when running the test bench. So I assume the problem lies in the way ModelSim simulates LabVIEW generated vhdl code. I was able, however, to run some simple LabVIEW FPGA testbenches in ModelSim. Thus, to further troubleshoot the problem I would suggest simplifiying your code. Once a simple version of your code can be successfully simulated in ModelSim you can add more components to it. That way we can identify where the problem starts occuring.

The good news is that I was able to run your code in Isim without errors. So that is definitely another option for you if you want to get up and running faily quickly.