Attempted to access DRAM Address 524288

[MrQuestion]

I see what you are getting at.

You can not rebuild it because labview doesn't detect a change in the simulation signitures. This is a big draw back to isim. In modelsim you can just recompile the test bench, but with isim you need an external program. I just noticed that in the "user" directory when compiled for isim a bat file is generated. This "RegenerateISim.bat" does not show up if you use modelsim.  This bat file appears to rebuild the simulation with the modified tb_NiFpgaSimulationModel.vhd file.

Double clicking on this should give you the approperate response in isim with the 4ms delay.

As for you files being modified on a recompile. That should never happen.

This is from "http://www.ni.com/white-paper/11574/en "

6.       Look at the folders generated in the simulation export directory.The ModelSim folder contains files used by the ModelSim simulation tool. You do not need to view or edit any files in this folder.The niFpga folder contains VHDL files generated by the LabVIEW FPGA Module to implement the simulation model. These files are regenerated each time the simulation export is built and should not be modified. However, some of these files can be useful later in the application.The user directory contains files that you can edit, including the top-level testbench file. In this case, the file is named tb_NiFpgaSimulationModel.vhd. This file is a template to implement a testbench and will be described later. This file is only generated the first time the build specification is built and will not be overwritten by the LabVIEW FPGA Module. A copy of the template is generated on each build in the niFpga directory for reference.

[Kevin_H.]

Great tips! Thanks! I ran the simulation with the wait from my compilation and didn't get any errors. I'm trying your source now and we'll see if it happens. If I don't see it this time I'm going to switch to ModelSim (unless you have other suggestions). Do you have another machine you can try this on? Just so we can be sure it's not machine specific. Additionally, if I change the simulation resolution time will it effect the result? Stepping ~1ps at a time for 4ms sure does take a while to finish executing!

Kevin Horecka | AENIC

[Kevin_H.]

Yayy! Got the error in modelsim 6.5c! Ok I'm going to test it in a later version of modelsim then I'm going to escalate it up the chain and see what information I can find on it.

Kevin Horecka

[Kevin_H.]

Hey,

I just wanted to update you that I'm waiting on a response from the escalation. Sorry about the wait! The recreation I made wasn't very stable. The error would only happen occassionally. Hopefully R&D will come back with some useful suggestions!

Regards,

Kevin Horecka | AENIC

[T-REX$ · Accepted solution]

Looks like there is a bug with our simulation model for the FlexRIO DRAM. It currently does not handle partitioned memories (which didn't exist when the model was created). Its a little nasty, but a workaround would be to create one large memory item (per DRAM bank), and create some wrapper VIs to partition it for you if you want to access it like it is several smaller blocks.

You should see your simulation pass just fine if you remove memory items B & D from your project/VI. This is definitely a bug on our side, and hopefully we can get it ironed out sooner than later.

[MrQuestion]

Thank you,

This is what I have expected from the begining.

Could you answer the following questions?

Since the memory is partitioned; will the user be able to specify memory location? This is important because many of our traditional FPGA projects go through a much more rigorous release process than what LabVIEW can currently handle, and one of the required parameters is knowing the memory map.

Will the partitioned size still have a lower limit?

Will the code synthesize correctly?

Regards,

[T-REX$]

Hello,

The code will still synthesize fine, and yes there will still be a lower limit for memory item size. There is currently not a way to force LabVIEW to use a particular memory bank, so there isn't a way to get a memory map that I am aware of. It does sound like a good candidate for the FPGA Idea Forum. We do actually use the forum when we are doing feature planning for our new releases, so thats currently the best way to get your requests into the hands of developers.