Cannot read data in FPGA

[RedAG]

Hi guys, I have a code that I developed for reading in digital data through digital lines in a PXI-7813R. But unfortnately, in the Host vi, I cannot acquire any data, even though I have fed in an external signal to the digital line in the PXI through a connector.

I have a data graph to display this signal, but nothing can be seen when I run the problem! Anyone know what the problem is?

I have attached the project.

ANy help would be great.

Thanks, Anoop

[nathand]

Have you debugged this code? Set the FPGA VI to run in simulation by right-clicking on the FPGA target in the project, and choose Execute VI On -> Development Computer with Simulated IO. Run the host with execution highlighting and you'll see the problem.

"Read?" is initially false so no data is put in the FIFO. As a result, the FIFO Read returns an error. That error causes the Read/Write Control node not to execute, so "Read?" will never be set to True and there will never be any data.

[RedAG]

Hi, thanks for the reply.

There is no such option for me on my project, but there is an option to run an 'Emulator', which I think serves the same functionality as the option you mentioned. I can set the 'Emulator' to read in random inputs. I have tried this, but the results are the same.

When you mean "Read" is initially false, do you mean that the control I used for it is set to false?

[RedAG]

I had set the "Read?" as switch, which when pressed, will read data. Is this not correct?

[RedAG]

I just noticed what you mean! Why does it automatically go to the "false" case? How do I set to a switch that I can choose so that it can go to the "true" case?

[RedAG]

I corrected this, but the same problem shows up. The "Read?" in the FPGA VI is a switch when pressed, goes to the TRUE state, but the data doesn't get read in the HOST VI even if I set it to TRUE in the FPGA VI and when I set the Emulator to random input.

I have attached the file to show what I mean.

[.aCe.]

You have set the read in the target to be 'True' so when a loop executes, the host which is set to false will make that false in the next iteration. But before you address that there are couple of issues in your program.

1. You are expecting to read 1000 samples and your target is not producing that many(as you are running it on a simulated device, your actual device may be able to do this) in the time specified so it flags up a timeout error 

Error -50400 occurred at Invoke Method: FIFO.Read in Host.vi

Possible reason(s):

NI Platform Services:  The transfer did not complete within the timeout period or within the specified number of retries.

You need to make sure that you have that many samples or wait for long enough to acquire that many.

Look at this link for some pointers: http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_dma_program_architect/

Also make sure you wire your error in to the while loop stop condition, otherwise it will just loop through without doing anything. Include a polling delay as specified in the link above.

2. In your vi, you are writing your read flag after the FIFO read, I would do this before that and in the host VI use a case structure to skip FIFO read if the read flag is false.

Hope this helps.

[RedAG]

Hi, thanks for the reply.

I have a couple of questions though. I dont understand what you mean in the first line. I have set the READ in the FPGA VI to be true so that when it is pressed, data can be read from the HOST VI.

Now, getting on to the issues you highlighted.

1. I have included a polling delay and the error issue is now sloved. But, when you mean "Also make sure you wire your error in to the while loop stop condition....", I have did this using the polling. Is this OK?

2. You mention "In your vi, you are writing...." do you mean in the FPGA? If so, I have set the "read?" flag on the case structure, to use it as a switch for teh true conditon. is this not correct?

I have attached the modified Project along with this. Feel free to edit it if you feel the urge too

[.aCe.]

I have edited your earlier version.

Have a look.

[RedAG]

Thanks, unfortunately, my LabVIEW is 8.5 and hence cannot open your code. DO you mind posting a Picture of both the files please?