Case structure on design and simulation loop

[YukiWong]

Dbohls,

Thanks you for your help dbohls, 

is that mean when a collector is used, must let the simulation loop run finish first only the graph got the result?

I had opened the file u attached, and i found something i not understand, what is the purpose of putting the halt simulation inside the control and design simulation loop and why the ring outside the loop is not equal to the ring then halt the simulation?

[dbohls]

The collector block does not produce output until the final step of the simulation. The simulation must end either due to reaching the final time or due to a halt block stopping the simulation. Only then will the collector block output all the collected data.

Now regarding the ring. You have to understand dataflow programming. The wire coming in from the ring will retain the same value while the simulation loop executes. This is the same as a tunnel on a for loop or while loop. The global variable outputs the current value of the ring every time the simulation does another loop. So, we are reading the ring value and test to see if the value has changed from when we first entered the sim loop. If it has changed, then the halt simulation block gets a true and halts the simulation. We then exit the sim loop, exit the case structure, and then the while loop does another iteration that takes us in to the other case for the new ring value.

[dbohls]

Yuki, I suggest you use LabVIEW's debugging feature to single step through the code and put probes on wires. Watch the execution order and how values change. This is something that should help you understand what is going on without having someone feed you the answer.

[YukiWong]

dbohls,

Okay, thanks for your advice dbhols. thank you very much 🙂