Control FPGA state machine from the host

[Cobmetal]

Hi,

Im writing a code , HOST and Target side for reading a binary file to the DRAM ,

each file has its own start address to be written in the DRAM , and is control from the host side. Im experiencing a strange issue , the first file is written to the DRAM with the initial address which i need , and i also able to read it again from the DRAM , but when im trying to load another file to the DRAM and read it (different initial address than the first) , im having an error .

the strange thing is that the first and the second address is the same everything is working great , but that is not what i need hhh.

need your help guys , im stucking with that issue for more than a week.

[GerdW]

Hi cobmetal,

so you have a problem with your VIs, but you don't attach them.

You get an error, but you don't name it (or tell about the error number).

What kind of help do you expect?

[Cobmetal]

ofcourse you are right , uploading them now.

thank you.

[GerdW]

Hi cobmetal,

now the project file (holding all relevant FPGA definitions) and several subVIs are missing…

But maybe your problem originated from using way too much local variables?

Suggestion: Learn to use AutoCleanup. Cleanup more often…

[Cobmetal]

I think the problem is that i can update the “init adr” variable , when im loading to the dram the second file , i cant say for sure wherever the problem at host or target logic

[crossrulz]

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@Cobmetal wrote:

I think the problem is that i can update the “init adr” variable , when im loading to the dram the second file , i cant say for sure wherever the problem at host or target logic

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Seems reasonable.  So move the reading of those controls into the Wait For Trigger state and store the values in shift registers.

[Cobmetal]

can you please give an example of waht do you mean ?

Best regards.

[crossrulz · Accepted solution]

Here is a cleaned up version of your VI.  Much easier to follow the logic when you organize things properly.

[Cobmetal]

Hi ,

Im really appriciate your help , i will check this as soos as possible , just another question , why do you removed the DRAM retrieve Data and Target-To-Host Write ?

[Cobmetal]

Hi ,

Just ran your code , and it seems fine but with some bug , im trying to read 3 files from the host using the dma to the dram , and then read the date from the dram through the dma to the host . when im trying to read the first file from the dram using the dma , the file isnt read fully , the next two are read full. when im trying to read from the DMA (Targe-to-Host) , at the first iteration in the elements ramaining i see only half of the elements, in the next second , i see the other half .

why is that ?

in the next two other files i see right number of elements remaining .