Downloading array of data to FPGA through DMA FIFO

[prashiit]

Hello

            I have to download array of 100 elements to FPGA. Each element in the array is added with 5. the resultant array is the fpga output.

  How can I achieve this with DMA FIFO. how many DMAs should be used for writing to FPGA and for reading from FPGA.   In my VI I have put two DMAs one for writing and another for reading.  I tried to write array of elements to DMA fifo in host VI.  These elements will be given to FPGA vi through DMA FIFO Read.  I connected the output of DMA FIFO read to a adder to add them with 5. I created another DMA FIFO (target to host). I connected the resultant array to target to host DMA FIFO. But, When I drag this target to host FIFO in host VI, I should get DMA fifo read. But I am getting DMA FIFO write.  It means there are two DMA FIFO write in host vi. and one fifo read, one fifo write in fpga vi.

 How can I read data from FPGA VI       

Please clarify

Thanks

Prashhhh

[COMSIS]

Hi

Prashhhh Have u properly configured the FIFO's in Host Vi using invoke method property. I don't think so dragging is a proper way to access the FiFOs in Host vi. All u need is connect the Fpga initializer vi to invoke method in Host Vi. Right click the invoke method first configure the both FIFOs and then configure the write and read property of FIFOS same way .Ur Host vi might look like this attachment.

 Regards

[prashiit]

Hi Comsis,

           Till now, I have put FIFO with read and write mode but I haven't configure them first.  Thank for your image. 

     If it is 100 elements, we can do in this way . But, If I want to process 65536 elements.....how can I do?  Actually, I am working on Image processing.

I am converting the image into 2D array. Now, i have to process this 2D array. I am getting so many problems in doing this. Here, Images are U8. Assume that image is 256*256.  Now, how should I send these data. 

 Can I use for loops for FIFOs so that for each iteration  I can send 256 elemtns to FIFO.  But, how should I do timing between FPGA VI and host VI.

For each iteration host VI should send 256 elements to FPGA VI. FPGA VI do some process and send the data to host VI. All these should be completed in one iteration. Again, in the second iteration, 2nd row ( another 256 elemtns) should be sent..............so on...

But, how can I synchronize both the VIs.    What value should I put for timeouts......?

[COMSIS]

Hi

1- if u want to process more element like more than the allowed depth of FIFO u can use  for/while loop for reading and writing in Host vi with a shift register for refrence vi's that will take the next max allowed element to get read and write and so on... .set the read FiFO timeout to -1 so it will waite until data is available to read(timing issue) .

2- As long as time out in FPGA is concerned it depends on ur real time Hardware ur using for just a try to give 10ms.   

Regards