Exposing XNET interface from RT to PC

[DonneyF]

Hello,

I have the following hardware: cRIO 9067 and NI-9860 XNET module with CAN tranceiver cables. I am working with a LabVIEW project that interfaces with the 9860 module. Right now, if the main VI runs from the RT target, everything works fine. The VI can identify the CAN interfaces and read/write to the bus.

I now need to integrate this project with another project that also interfaces with the cRIO. To communicate information between the PC host and the cRIO, the project uses sub VIs (no shared variables). In this way the user only needs to run the VI targeted for the PC.

If I try to have my RT VI as a sub-VI on the PC VI, then the program can no longer identify the CAN interfaces, since the dependency on my RT VI is referenced under "My Computer" rather than the RT target. I believe it's trying to identify XNET interfaces on my PC rather than on the cRIO.

Is there a way for me to expose the XNET interface to the PC while allowing the RT VI run as a sub-VI from the PC? The work around (I guess the "proper way" of interfacing with the RT VI) is to use shared variables, but I would rather not rewrite an existing code base that has proven to work.

For extra clarity here is the project structure for before and after:

VI Runs from RT (Works)	VI Runs from PC [RT Sub-VI] (Cannot find XNET interface)
My Computer NI cRIO 9067 RT Main.vi	My Computer PC Main.vi Dependencies RT Main.vi NI cRIO 9067 RT Main.vi

Thanks!

[rolfk]

I don’t think that’s possible. VISA resources can be shared like that and accessed remotely from another system but XNET is not based on VISA.

You’ll have to write some explicit code. Personally I wouldn’t use shared variables for this but your mileage may vary. If it is something you have already experience in it may be the easiest and quickest solution.

[DonneyF]

Hey Rolf,

I'm fairly new to the cRIO and XNET platform and I'm not sure what would be the best solution here. I'm currently using shared variables to pass tell the RT VI to start/stop and communicate data with the PC VI but I'm not sure if that would be the best solution.

Do you have any pointers?

Thanks!

[DonneyF]

I'd also like to reiterate that this is the functionality I'd like to achieve: https://learn-cf.ni.com/teach/riodevguide/guide/rt-pc_inter-target-communication.html

• The PC host and the RT target execute the same VI on two systems: PC runs the front panel, and RT runs the block diagram
• Data flows between the PC host and RT target through the Academic RIO Device network connection (either USBLAN or wireless) in a way that is completely transparent to the developer

Right now I can communicate with the FPGA without having to explicity run a RT VI. I open the XNET-enabled FPGA reference, but the VI is unable to find the XNET interface.