Extracting I & Q phase component in labview FPGA

[mcduff]

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@DeepakDSPEngineer wrote:

Please tell me, What is the redfilterDataIn here. Will I need to pass the IQ Demodulation signal to any filter again? 

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I used multiple parallel loop to do the demodulation; remember when you do it this way the first set of samples will be garbage, for my application I did not care.

Each loop is connected with a FIFO queue.

1. Loop 1
   1. Signal Input
   2. Sin/Cos generation at the carrier frequency
   3. Multiply the signal by sin/cos
   4. There is a high pass filter to remove any DC low frequency components before the multiplication/mixing
2. Loop 2
   1. Low Pass filter to get I & Q
3. Loop 3
   1. Do the demodulation by unwrapping the phase

This was on a myRIO that has limited capabilities. The output of the phase unwrap was then sent to filter that reduced the output rate. The demodulation output rate was about 30kHz, I reduced that to 7.5kHz using a filter.

mcduff

[Deepak.k]

Hi Mcduff,

I want to do all the things in Single Cycle Time Loop. So, Filter is not working in that loop, Please suggest me something. by which it can work.

Or If you have any supporting documents of it. Please send me ..my email id is dsp26976@gmail.com. 

Thank you.

[mcduff]

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@Deepak.k wrote:

Hi Mcduff,

I want to do all the things in Single Cycle Time Loop. 

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Why is this a requirement? Some things cannot be in a SCTL, nor do they need to be done in a SCTL.

Suggestion: Think about your requirements, frequencies, FPGA space etc. I am chemist not a DSP person, so sorry I cannot help you more.

mcduff

[Deepak.k]

These are a lot to me. Thank you so much for your help.