FPGA 2009 table search

[lmd2]

running LabVIEW 2009.0f2 (32 bit) with a cRIO. In LabVIEW I have a FIFO input where I read a byte, and I need to look for a match in a table (block memory). can anyone point me to an example doing something like this. I seem to be having a hard time finding examples of memory manipulation on an FPGA.

thanx

lmd2 

[Anna_K.]

This is a good place to start.

http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgahelp/using_memory_fpga/

Are you using block memory or a lookup table?

[lmd2]

Hi Anna

thanx for the response but I was hoping for an example that could optimize searching for a match. Specifically my FIFO will be a stream of bytes, after say a dozen clock ticks I will have data in a dozen registers. Then I want to search a table of data in block memory (or a look up table) for a set (or row) where elements 2,3,4,6,7,& 11 match registers b,c,d,f,g,& K

I don't expect to find an example doing exactly this, but I can't seem to find any examples of searching memory on an FPGA, using on-chip look-up tables, ... I can grasp the concept, I know that it is doable, but I don't know enough to figure the best approach or even what my options are; and there doesn't seem to be much out there for guidance

thanx anyway

lmd2 

[lmd2]

actually if there aren't any examples doing a search and match,

maybe someone could point me to a white paper or tutorial on using look-up tables on an FPGA, or any related material on how to efficiently search memory?

thanx

lmd2 

[Anna_K.]

Hello There is a an example in the example finder calling Using a LUT - cRIO.lvproj that uses the Look-Up Table 1D Express VI . The other options are to creat a Memory item on your FPGA ( right click the FPGA target and select New >> Memory ). The main differences between an LUT or Block Memory is that Block Memory is large but slower and an LUT is fast ( can execute in one clock cycle ) but can fill up faster. If your data is larget than 1kB, use block memory, but keep in mind it will likely take mutiple clock cycles. There aren't really examples of this, but they are pretty straight forward, mainly used the same as an array. Let me know if you have questions

[lmd2]

thanks, I'll check out the LUT example - the speed factor sounds great but size may be an issue. my dynamic input (FIFO) will be 16 bytes read as two 64 bit numbers (so two clock ticks). out of those 128 bits some will be one-bit flags, but some will be ASCII (bytes). The static memory (LUT) will hold dozens of sets, each set maybe 20 bytes and I need to search for the set that matches a subset of those dynamically acquired ASCII characters. I am sure that I can code this, but I am just as sure that it won't be optimized (I am a LV architect, but am still new at FPGA coding) - was hoping for a slick example, guess I'll just have to wing it.

Thanx for the info

lmd2 

[Anna_K.]

If I may, we do offer FPGA Training courses that are extremely useful to learn the technology and how to weild the power of FPGA. Check out the NI Training Locator if you are interested.

[lmd2]

I am fighting to get that into our budget, just a matter of time