FPGA Compilation Fails due to Xilinx Error

[James.M]

My FPGA won't compile and I can't figure out why. There is nothing crazy in my FPGA VI really, so it seems strange to have this type of problem. I can't attach the code because it proprietary, but it is pretty simple in that it reads all of the channels from a single module and writes them to a data FIFO. I have successfully compiled other FPGA code on this computer, so I should definitely have everything necessary to compile.

My system consists of an NI cRIO 9030 with a single 9220 module. Below is the Compilation summary.

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LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:295]
ERROR: [Synth 8-1031] knidmahighspeedsinksize is not declared [/opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:296]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:301]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:302]
INFO: [Synth 8-2810] unit pkgshimswitchedlinkdmaportifc ignored due to previous errors [/opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/PkgShimSwitchedLinkDmaPortIfc.vhd:68]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:31 . Memory (MB): peak = 798.605 ; gain = 204.203
---------------------------------------------------------------------------------
ERROR: [Common 17-39] 'source' failed due to earlier errors.
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
::ERROR: [Common 17-39] 'source' failed due to earlier errors.

while executing
"source -notrace ./.Xil/Vivado-6035-ip-10-60-203-176/realtime/toplevel_gen.tcl"
invoked from within
"synth_design -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "/opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/synthesize.tcl" line 21)
invoked from within
"source "/opt/apps/NIFPGA/jobs/mC683d5_WCf98Qm/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Tue Mar 24 23:58:54 2015...

Compilation Time
---------------------------
Date submitted: 3/24/2015 4:46 PM
Date results were retrieved: 3/24/2015 5:00 PM
Time waiting in queue: 00:24
Time compiling: 13:22
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 01:27

Compilation was restarted on
3/24/2015 4:57 PM

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Any help would be highly appreciated!

Thank you,

[natasftw]

How close are you to your max resources?

Are you in FPGA mode or hybrid?

If you use just one of the I/O you mention, will it compile?

It's going to be difficult to help without the code.  I hope you're coming into this with that expectation.

[Eric.M]

Can you try with a smaller DMA FIFO ? You can also try recreating the FIFO from scratch. This kind of issue with Vivado is under investigation by Xilinx and NI. Also, if the code is this simple (with no proprietary algorithm or such), can you please attach it so that it can be tested by other people ? 🙂

Thanks,

--Eric

[James.M]

---

@natasftw wrote:

How close are you to your max resources?

Are you in FPGA mode or hybrid?

If you use just one of the I/O you mention, will it compile?

It's going to be difficult to help without the code.  I hope you're coming into this with that expectation.

---

Thanks for the replies!

I am not anywhere near max resources. The Compilation fails before it gets to the resource estimates, so I don't know the numbers.

FPGA mode

I tried compiling with no FIFO or not module IO, but it still failed.

I removed all proprietary algorithms and have attached the source VI.

Thanks for the help,

[Eric.M]

Hey James,

I successfully compiled your VI. Have you also tried to recreate your target (cRIO and FPGA) in your project ? The Xilinx error you got seems to pinpoint missing signals in the vhdl. This can result in warnings, but these signals are mandatory and may be the result of your FPGA target being corrupt in the project...

[James.M]

---

@Eric.M wrote:

Hey James,

I successfully compiled your VI. Have you also tried to recreate your target (cRIO and FPGA) in your project ? The Xilinx error you got seems to pinpoint missing signals in the vhdl. This can result in warnings, but these signals are mandatory and may be the result of your FPGA target being corrupt in the project...

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I deleted the target cRIO and FPGA in my project and recreated them both from scratch without even the physical device connected. I still get the same error unfortunately.

This code was inherited from our client and was originally LV2011, so I think the next step is to create a project from scratch completely and see if that fixes anything.

Thanks,

[James.M]

Alright, so it looks like I'm getting the error with a project from scratch and an FPGA with a single control and indicator.

I'm downloading the latest FPGA 2014 SP1 install and hopefully that will fix my problem.

[James.M · Accepted solution]

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@James.M wrote:

Alright, so it looks like I'm getting the error with a project from scratch and an FPGA with a single control and indicator.

I'm downloading the latest FPGA 2014 SP1 install and hopefully that will fix my problem.

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Well I'll be darned, that fixed the problem! Somewhere along the line, my FPGA install must have corrupted.

Thanks for the help, guys.

[Ben_Engelen]

I am having the same issue here, but installing the latest FPGA 2014 SP1 did not fix my problem!

Other things that can be checked/done to get this working?

[bets855]

I am also in the same boat! I have uninstalled and reinstalled LabView 2014 SP1 and I am still getting this error. Does anyone else have any idea as to why this is happening? 

Thanks to all!!