FPGA Memory Config

[meBaga]

Can any body Give me proper Idea about this? I want to understand the logic of this selections. 

1. What does it means by "Arbitration" here ?

2. What is this "interface A & B" ?

3. Using the memory in multiple clock domain means what ? My FPGA is having one 40 MHz clock multiple clock domain means what? RT & FPGA ??

[thoult]

The arbitration options reserve resources during compilation to manage access to components from parallel processes.

Say you have a memory item which is accessed in one loop in your FPGA code. You read from the memory location, do something, and then write back to it a couple of times depending on something else. Relying on dataflow, or using flat sequence structures to enforce execution order, there's no need to arbitrate because all operations are sequential.

Say you have a memory item which is accessed in two loops of the FPGA code. Arbitration is required to control one-at-a-time access to it.

For an overview of arbitration, have a look here. The options are better explained here.

If you're trying to access the memory location across two clock domains on the FPGA (e.g. your master 40 MHz clock domain and a derived clock at a different frequency), such as reading in a SCTL in one domain and writing in another, you'll need to enable the interface for this. The two interfaces are the read (A) and whatever you set B to.

Hope this helps.