FPGA PID data type Conversion

[chi_visor]

Hi. I'm facing a situation where the AO module(NI 9263) that i have, can support (+-20,5) but the output of the FPGA VI supports only(+-16,8). Can anyone elaborate a little more on scaling and how to do it effectively without loss of precision in the output?

Is there any specific reason for the PID output to be (+-16,8)? Why cant it be of higher resolution?

One more question: I'm running the PID loop at 200us and when i set this sampling time (Ts) in the FPGA PID express vi it auto formats to 0.00s. I'm assuming it sets to 200us internally. Is that correct?

Thanks & regards,

Chirag.

[chi_visor]

Hi. I'm facing a situation where the AO module(NI 9263) that i have, can support (+-20,5) but the output of the FPGA VI supports only(+-16,8). Can anyone elaborate a little more on scaling and how to do it effectively without loss of precision in the output?

Is there any specific reason for the PID output to be (+-16,8)? Why cant it be of higher resolution?

One more question: I'm running the PID loop at 200us and when i set this sampling time (Ts) in the FPGA PID express vi it auto formats to 0.00s. I'm assuming it sets to 200us internally. Is that correct?

Thanks & regards,

Chirag.

[osvaldo.dias]

The first question that chi_visor asked about the resolution is related to my issue. Anybody knows how to increase resolution? I've tried to convert the PID FPGA VI to a subVI, but i couldn't reach satisfatory conversion.  

Thanks