FPGA SCTL won't compile with a slower clock rate

[Dave_Thomson]

    I have an FPGA program that used to compile, but is now saying that the SCTL is failing to complete in time. (https://forums.ni.com/t5/LabVIEW/FPGA-program-won-t-compile-any-more/td-p/4260960) One possible solution would be to run the loop at 20MHz instead of 40MHz, so I created a 20MHz clock and tried to compile. It gave a long list of items that are not supported under a SCTL! Another solution is to simplify the math, removing one operation. Doing that, I got the code to compile at 40MHz. In a SCTL! So why can't it also compile at 20MHz?

TIA,

      DaveT

(The attached image shows the SCTL configured at 20MHz. This same VI (which has the math simplification) compiles when the loop is configured for 40MHz.)

[Jacobson-ni · Accepted solution]

I don't remember where I saw this but I believe if you are using the FPGA on a c-series chassis and accessing DIO, that DIO is not accessible in arbitrary clock domains (I believe you can only access the I/O in multiples of 40MHz).

[Dave_Thomson]

Ouch! That could definitely be the problem. I've never heard that before... Thanks for the info.