FPGA analog input rate

[shuishen1983]

Thanks, I will look at the DMA and FIFO examples, and will let you know if it works.

[shuishen1983]

I am trying to duplicate the DMA FIFO tutorial in NI Developer Zone. On page 2 there is a block after the I/O node, which then goes into a For loop. I think it is Initilize Array, but the one that I have for Initilize array looks different from this one. And the data type changes to some unknow type when it goes through the Initilize array block on my computer.

Besides, the FIFO write/read block in the for loop looks different too. It does not have a "Data" input port and a "Full" output. Instead it has an "Element" port and a "Timed out" port. Am I using the right block? Or my Labview version makes those blocks looks different? My version is Labview 8.5

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You cannot get LabVIEW to plot the data with real time on the X axis automatically.  You need to set the scale factor to match the rate at which you are acquiring data.  LabVIEW will simply add one new point to the plot each time it gets new data, regardless of actual loop rate.  That also means that if you have a gap in the data acquisition - say, Windows switches to doing sometime else for a second - you won't see that in your graph.  In order to get consistent timing you need to use some sort of hardware clock.  In your case the FPGA can do it if you use a DMA FIFO to transfer the data, but not if you use a front panel indicator as you are currently doing.

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[nathand]

Please link to the example that you're following.  You are using the right block.  It sounds like that's an old example (the FPGA FIFO functions have changed) and you should find a more recent one.

[shuishen1983]

http://zone.ni.com/devzone/cda/tut/p/id/4534

Here is the tutorial.

I down load two files concerning this DMA FIFO. I now know I should use Build Array block. But still I can not connect Build Array to FIFO read/write. The error showns that the source is I16 but the sink is void. However, In the examples, I find out that the data type problem doesn't exist. And the data type from I/O node is not 16 bit. Instead the line color is gray. How can this happen?

[nathand]

Did you create the DMA FIFO in the project?  If not, then you'll get an error about the sink being void.  In the project explorer, right-click your FPGA target and choose New->FIFO.  Set the type to Target-to-Host and set the data type to match the type of data you're reading from the analog input.  Then select that FIFO in the FIFO Write method on the block diagram.

[shuishen1983]

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@nathand wrote:

Did you create the DMA FIFO in the project?  If not, then you'll get an error about the sink being void.  In the project explorer, right-click your FPGA target and choose New->FIFO.  Set the type to Target-to-Host and set the data type to match the type of data you're reading from the analog input.  Then select that FIFO in the FIFO Write method on the block diagram.

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yes, I did create the FPGA FIFO, I selected Host to Target -DMA for type and DMA Channel 0, Depth 4095. But the Data type is gray, so what I have is U32 instead of I16. I think because the data type difference. I can't link them

By the way, the Read Attributes is: Arbitrate if Multiple Requestors Only.

[nathand]

The gray wire is fixed-point data.  You can see the data type by turning on context help (control-H) and putting the cursor over the wire.  However, if you were previously reading integer data and now you're reading fixed-point data then you probably have not properly configured your IO channels (I'm guessing you copied an example but didn't change it to reflect your actual hardware).

[shuishen1983]

I copied the FPGA FIFO write block from the example to my own project, the color of the fonts on the block is changed. Element becomes blue. It is also different from insert a block from the block library directly. The block generated in the latter way is all block, and the type of the data is void. Why this difference happened?

But there is a problem, the port traigle become red. What does that mean?

[shuishen1983]

Thanks, I have figured it out. But we are controlling the sampling rate through which constant. The number of points to read or the FPGA period or both? How does that work? If I want 10000 points in one second, how should I set the parameters.

[nathand]

The FPGA period determines how fast you are sampling the analog input.  Each iteration of the FPGA loop it will put a single sample per channel into the FIFO.  On the host, you need to read enough points to keep up with the FPGA rate; otherwise, the FIFO will fill and you'll lose data.  In order to get 10,000 points per second you need to run your FPGA at 100us.  On the host, you might run a 200ms loop and read 8000 points each time (4 channels x 2000 samples).

You can set a different size for the FIFO on the FPGA and on the host.  On the FPGA you don't need a large FIFO (I'd leave it at about 500 elements unless you're really short on space).  On the host, you want the FIFO depth to be sufficient to hold several cycles of data - say 40000 points for one second worth of data - in case something interrups the loop momentarily.  You configure the FIFO depth on the host using an FPGA Invoke node (see the LabVIEW help).