FPGA error when opening reference

[rex1030]

I am running the 8.6 and all the latest versions of the software on a cRIO device. In my RT code i am opening a reference to an FPGA file and when I do it times out with this error:

error code: -63192
 in Host CRIO Kyle.vi in Host CRIO Kyle.vi<append>
<b>FPGA activities:</b>

Reference open through FPGA interface. in Host CRIO Kyle.vi in Host CRIO Kyle.vi

There seems to be no explanation of this error on the NI website and I need help figuring out why the error might be occuring.  

[Mathan]

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rex1030 wrote:

error code: -63192
 There seems to be no explanation of this error on the NI website and I need help figuring out why the error might be occuring.  

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Quick search. I hope that error was well discussed. Please use translate.google.com for translation

[rex1030]

For some reason translators are blocked by surf control here at work so I don't have access to google translator services here.

Can anyone tell me how to fix this... in english?

[DanRichards]

Hi rex,

Looks like you're working with Rob Klein on this issue. I looked through the French discussion forum and saw that they don't actually ever answer their customer's question. It seems the customer gave up writing back about it. Please don't give up on your issue and keep Rob updated on your progress. When we come to a solution, we'd like to post that solution on the discussion forum so that others can benefit from it, too. It's nice to get that information at a click, right?!

Rob already mentioned the previous issue about improper addressing. There was another issue with this error that was solved by changing the resource name to IP Address:RIO0 instead of just RIO0. If you want to try to enlist more support from the online community, I would recommend sharing more information about your application, including screenshots of your setup and the error you're getting. I hope we can see this issue through to its solution.

Regards,

[rex1030]

Well I have been sick for the last couple of weeks and have not been at work. It looks like my support request timed out and I had to resubmit my request. Hopefully I will continue to work with Rob. We'll see. I definately have to solve this problem so I will be posting the resolution on this thread like you ask.

The project I am working on is pretty big and would take a lot of explaining. If you were more specific about what sort of information you would like, I could give you what you ask for.

[rex1030 · Accepted solution]

Ok so I made a stupid mistake. The project I am working on uses 3 crios simultaineously. To simplify things, all the cRIOs run the same VIs on them and where necessary, they detect what crio they are on the fly.

Well, because all the crios use the same file I had only been opening the file structure on the first crio in the project. The error occured because I did not have the FPGA files in the FPGA parts of the second and third crios in the project. Either they had gotten deleted, or were never added when I created a new project (created a new project to solve a previous error). So when the reference the the bitfile was attempted to be opened on the second and third crios, there were no FPGA files in the build so it would give this error. 

Quite embarassing.

[DanRichards]

Ah.. sounds like no fun. 🙂

So does that mean you've hit a solution?