FPGA pulse counter moving window

[Roli_89]

Hi, I want to realise a pulse counter on a FPGA Target. I included an example that works on the Host but I cannot compile the Sub VI for FPGA. My code seams a little bit too complicated could someone help me to streamline it.

The basic concept is that whenever there is a new pulse I save the “time stamp” in an array at the head index; if a “time stamp” gets too old, I move the tail index up. The difference between head and tail is the number of impulses in the time window.

Thanks!

Best regards,

Roland

[GerdW]

Hi Roli,

The basic concept is that whenever there is a new pulse I save the “time stamp” in an array at the head index; if a “time stamp” gets too old, I move the tail index up.

Using large arrays is not very "FPGA-like"…

What about this concept:

1. Determine pulse length by measuring "timestamp" of rising and falling edge (or two rising edges, when you are interested in pulse distance).

2. Store a fixed amount of those length values in a (small, like 8 entries) array to calculate an average for the last pulses…

What exactly do you need? Speed (pulses per time unit)? Or do you need additional data like speed variations (between pulses/ per rotation)?

[Roli_89]

Thank you for your reply. I cannot use that kind of scheme due to the sensor type. It is a flow rate sensor I expect something between 0 and 300 pulses per second. I have tried it before and I am seeing just a lot of noise. It is meant to count the pulses within a certain time period.

[GerdW]

Hi Roland,

I use such sensors a lot…

How fast does the volume flow change?

Anyway two suggestions:

1. Just count the pulses on your FPGA and let the RT part do the volume flow calculation. No limitations regarding array handling…

2. Count pulses on your FPGA and use a second (slower) FPGA loop to calculate volume flow by reading the counter value once a second (or similar intervals).

[Roli_89]

Mmh, all this seems a bit excessive for such a simple task. I have an array with 500 integer values at 100 us clock so 2400 clock cycles. Is the array really to large? Even if I would calculate the flow rate in another loop or the RT I would still need that array. Could you give me some advice how I can improve the existing code.  

[GerdW · Accepted solution]

Hi Roli,

see the first line in your error text:

Place Check : This design requires more Slice LUTs cells than are available in the target 
device. This design requires 59664 of such cell types but only 53200 compatible sites are
available in the target device.

As I said before: large arrays are not recommended in FPGA designs!

Having the same array in the RT host is simple: your RT target should have megabytes of RAM available to hold a simple array of 500 values (needing 2kB for I32 values)!

The largest array I used in a FPGA design was using 32 entries (for a very specific task handling specific hardware).

Otherwise you can try to use memory blocks instead, here I used rather small blocks of 256 FXP values (handling AI values of a NI9205).

Both options require you to learn about certain FPGA programming techniques - you cannot simply "drag & drop" a VI from your PC host to the FPGA…

all this seems a bit excessive for such a simple task.

IMHO you made that task more complicated then it needs to be…

[Roli_89]

Thank you, I belive I can solve the problem by using Memory blocks. I would very much like to learn FPGA programming techniques.