FPGA question (UP Cast)...

[Helmut_K]

Hi all,

I have following problem: We use a PXI 7831 R an implemented two FPGA.vi 's. My task was it to approach both FPGA.vi's with only one host.vi . These shoud be possible when you use the "Up Cast" module...

But I got the following errors in the error list:

- Block diagramm errors:

  - Wire: function conflict

     - refnum conflict: cannot connect different refnum types

Message Edited by Helmut_K on 09-30-2005 01:39 AM

[Ray.R]

Hi Helmut,

It appears that you are wiring the wrong refnum to the input of that vi, thereby causing a conflict.

Can you either post your vi, or at least a screen-shot of the code showing the portion where the refnum originates and connects to the vi?

Which reference are you using for the vi?  Because it appears that the refnum is of different data type, which means it is not the appropriate reference for that particular vi. 

Regards,

JLV

[Helmut_K]

Hi Joe,

sorry for the late answer, but i was very busy 😉

The problem still exist and so I attach a picture of my LabVIEW code. In the picture you will see the wire conflict. The second case was similar to the case on the picture. I only changed the name of FPGA file... (so also the frontpanels of both FPGA VIs are identic and so in my opinion also the refnum should be identic)

If someone has an idea what kind of problem I have to handle I will be pleased.

Regards Helmut

[Ray.R]

Hi Helmut,

It appears that the reference type is different for the other FPGA. 

Are typecasting the other FPGA reference? Basically, they should match types.  I see the PXI-7831R.  It is passing a cluster of refernences. Are these references identical in type to the one not shown?  Am I correct to assume that you created the sub-vi and created the reference by combining two or more elements?  If so, are the elements in the same order? 

Can you place a couple of probes in your block diagram and re-post the same picture? 

Proble #1:  between the PXI-7831R sub-vi and the generic class reference.

Probe # 2: between the Case Structure and the Property Node.

Probe # 3: to the right of the generic class reference (where the red "X" is). 

I suspect two things, either you are not using a generic class in the other Case, or the target class is different, or the elements of the reference cluster are not in the same order for the two clusters.  I am not sure what happens when a target class is wired in one case but not the other..

However, the probe will show the contents of the clusters.  They should match.  If they don't, you can look for the source of the mismatch. 

Hope this helps,

JLV

[Helmut_K]

Hi Joe,

first of all, thanks for the help...

Now I have attached two more pictures with the probs and moreover a context help window where you can see the cluster exactly.

When I start with that VI some of your proposals are responsible for the failure. First I have not typecasted the other FPGA reference. And later I found another failure which occure because the two FPGA VIs have different "Connector Pannels". But these two failures are now removed...

Now I have checked both clusters and in my opinion they are absolutly identically (you will see both in the two pictures).

I hope the new picture would help and thanks for your replies.

Regards Helmut

[Helmut_K]

The second picture...

[Ray.R]

Hi Helmut,

As I suspected, the elements of the reference clusters are somewhat different.  It would be nice to see a probe on the broken wire (red-X).

The probes 2 & 6 match.  The contain the Execution Reference and the Execution Target. 

Why do you need the Connector Pane & the Front Panel controls as part of that cluster?  Would it be possible to use the reference cluster without the "Generic Class Reference"?  In other words, connect the output of the PXI-7831R directly to the output of the Case Statement? Since they match, that would resolve the broken wire.  I simply do not know if you need to use the connecor pane & front panel controls.  I doubt it 😉

Try removing the Generic Class Reference.  For some reason, it appends the front panel & connector pane to the reference cluster as shown in the 2nd image (probes 3 & 7).  I suspect the elements should be similar to probes 2 & 6.  Well actually, I am more familiar with a single reference which in this case would be the Execution Reference (only), typically a blue-green wire.

The first step is to resolve the reference cluster mismatch.  They must have the same number of elements and the same types at the same locations.  Without seeing the complete diagram, I cannot recommend using the execution reference only.... but it might be worth a try..  😉

I am curious at what are the elements of the cluster at the broken wire. 

Hope this helps.

Regards,

JLV

[jdigiova]

I have attached a simple example of using the upcast function. Important notes are that the front panels of all FPGA VIs are identical. You should also wire the error terminals from the Open FPGA Reference to the error terminal of the upcast function. This will ensure they stay in sync. Please test the attached program and make sure it works on your system. If possible can you include your code, rather than screenshots? Regards, Joseph D. National Instruments

[Helmut_K · Accepted solution]

Hi,

the problem is solved

My problem was following: Of cource, I use identically FPGA VIs but these files are attached to different projektfiles. So it is important that both FPGA VIs are in the same projektfile.

Moreover it is important to check the front pannel and collector pannel because it is necessary that these pannels are absolutly identically. (--> indentical clusters) 

THX to Joe and Joseph (for the very helpful example) because without your help I don't think I had found the failure...

Regards Helmut

Message Edited by Helmut_K on 10-06-2005 10:26 AM

[Ray.R]

You're welcomed..  🙂

It is also nice to know that the Front Panel & Connector Pane have to be part of the cluster reference.  And yes, clusters must be identical when wired together.

JLV