FPGA question on speed

[tomnz]

I have as part of much bigger problem to simply multiply the elements of two arrays and sum the terms to give a single constant output.

There may be say 100 terms in teh array but this test I attach only uses 6 numbers and uses the same array twice for simplicity. I am therefore calculating the dot product of two vectors X'X where ' is transpose.

It was suggested that I split the calculation in half so that I sum the first 3, ie 0,1,2 and last 3, ie 3,4,5 in parallel (as in the program). I of course get the same end result. Would this double the speed of the FPGA execution because it is doen in parallel?

The reason I ask this question is that surely if I used a power of 2 for the amount of data I could split it up again and again a bit like an FFT,

Does this make sense? or does the FPGA "unwrap" the FOR loop anyway so it is not worth the effort?

the program shows the orginal and the split method.

Thanks

[MarcoMauri]

On FPGA two loops running in parallel and summing 50 numbers each

need 50% of the time needed by a single loop summing 100 numbers.

You save time,

you spend space (on the FPGA).

Regards,

Marco

[DFGray · Accepted solution]

The up side is that an FPGA will give you speed gains every time you parallelize computation.  The down side is that you still need to do most of it yourself.  No currently shipping NI FPGA product does optimizations like loop unrolling (although standard LabVIEW does).  This is an unsafe operation that could increase code size and FPGA programmers tend to be picky about such things.

So you can get speed gains every time you parallelize, but you will have to do it manually.  Note that if your parallel loops are accessing a shared resource (memory, state variables, etc.), contention over this resource will reduce the overall speed you get as a result.  Also, if you can imbed calculations in a single-cycle timed loop, you will get efficiencies there, as well.

Good luck and have fun!

[MarcoMauri]

"Also, if you can imbed calculations in a single-cycle timed loop, you will get efficiencies there, as well."

You cannot place a for loop in a single-cycle timed loop.

It's a pity 🙂

[nathand]

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MarcoMauri wrote:

You cannot place a for loop in a single-cycle timed loop.

It's a pity 🙂

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No, but you can use the iteration counter of a single-cycle timed loop, and set an appropriate stop condition.  You can always replace a for loop with a while loop.

[tomnz]

Is it better to use reentrant subs for repeated code or just write the g code explicitly.

Thanks

[nathand]

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@tomnz wrote:

Is it better to use reentrant subs for repeated code or just write the g code explicitly.

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From a performance point of view it makes no difference, so it's probably better to use subVIs to make the code more manageable.  My understanding is that there is no overhead to calling a subVI in FPGA if no arbitration is needed (the subVI is reentrant or called only once) - such subVI calls are inlined during compliation.