FPGA rational resampler

[Frid.Martin]

Hi!

Im working on a project and I use a compactrio 9040 with 4 x NI 9224 modules. I wish to resample  data from the modules from 1000 S/s to 20 S/s using the rational resampler on the fpga. But it does not work as I want, it seems like my output data is rather ~22 S/s.

My question is if  I use the resampler and FIFO incorrect somehow?

Currently I wait for the outputvalid signal before sending it into the FIFO, is that the correct way to deal with?

Please see the attachments.

Best regards

Martin

[cbutcher]

Hi Frid,

Nothing appears (at least to me) to be wrong with your resampling setup, so I wonder if one of the following is true:

• The input is being delivered more frequently than 1000 times/second (even though the sample rate of the modules is 1kHz max) - maybe you're delivering duplicates and not waiting for new samples? (the outer loop, not visible in your screenshots, would be what to consider here)
• You're measuring the ~22 S/s wrongly (I'm sure you were careful here, but I'll point it out anyway just in case)

Is it possible either of those is true?