FPGA synthesis: "Error generated from encrypted envelope"

[tcachat]

Since the last message I could compile without error, everything was fine. Then last week I added a Xilinx IP and a few lines of code to my CLIP, then I faced again this "Error generated from encrypted envelope" associated to the name of one of my source files (.vhd). Again the line number does not help (because during the compilation the source is encrypted). After searching in different ways, I came back to the previous version of my source file, and started to add the modifications one by one. It seems to me that the present error is related to a syntax not accepted by the tools (possibly related to the fact that VHDL 2008 is not supported, as I read somewhere).

Possibly the first time I faced this error the reason was completely different.

[benjamin-hinrichs]

Although not related to your problem, I just stumbled on this error message today.

I was working on some dynamic dispatch code for FPGA and passing the initialized child object to a while loop with some case structures inside. When using a shift register it wouldn't compile. The same code using tunnels compiled fine.

The LabVIEW syntax was fine; it just wouldn't compile with xilinx tools