FPGA

[rira18]

Hi T-Rex$,

I'm so sorry, I wrote the name of the file between parenthesis in my last email but it was erased. You can find it in the Adaptive Filter Toolkits named "Fetal ECG extraction" but you need to have the Advanced Signal Processing Toolkits. After half hour I will complete the check up and I will communicate the feed back of the others propositions

You can also see the related link: http://zone.ni.com/devzone/cda/tut/p/id/11248

Kind regards

Rira

[rira18]

Hi T-Rex$

Sorry for the late to give you my feedback, because yesterday I had an error (to open the FPGA in the host) but I adjust it.

Now, the compilation was correctly done, but (hi, lo) in the FPGA fron panel still running until I stop the server. I tested  the acquisition of two identical signals in the two input from a generator:

1)      I can acquire only a squares signals in high frequency but when I change the form to the sinusoidal or I decrease the frequency I obtain this (please see the picture 1 bellow).

2)      Also I want to change the  x & y scale (I tried autoscale, change the values manually) but when I start the acquisition the very high values back

3)      I can’t see the signal shown in maternal graph only if I increase the amplitude (please see the picture 2 bellow).

I think that I have a problem in the rate processing or the rate sampling, by the way the last time I just tried to do the correct block diagram with many acquisitions and I thought to compute the necessary rate sampling and he rate of the processing in the second step, but now I realized that I was wrong by think in this way.

Features FECG: amplitude = 10 –100μV  and the FHR normally lies between 120 and 160 beats per minute (bpm) corresponding to a fundamental FECG frequency between 2 and 2.7 Hz. In pathological cases, the FHR may be outside this range, resulting in a fundamental FECG frequency around 1.3 Hz (fetal bradycardia) or 3.3 Hz (fetal tachycardia)

 Features MECG: amplitude = 0.5–10 mV  and the Heart Rate (HR) the maximum rate is around 100 beats per minute and the minimum heart beat is around 60 beats per minute that mean between 1 and 1,66 Hz  (HR=1/T = 1/RR (pic intervals) in Hz to obtain in bpm we have to multiply by 60).

I found in many papers that the rate sampling are diffrent values but I don’t know how they choose it? I thought that may be they used the Shanon rule? I found this in one of the related papers:

Definition of The RR Intervals: the implementation ofthis algorithm depends mainly on the normal heart rate (HR)and the sampling frequency, where the maximum rate is around 100 beats per minute and the minimum heart beat is around 60 beats per minute and the sampling frequency. Thesampling frequency is chosen 256 in this work.

And what about the processing rate, is it calculated by this rule:

 Rate processing= 1/ period processing which the period of processing = duration of the acquisition/ memory size?

[rira18]

Hi T-Rex$,

Oh so sorry, really I forgot to told you that as we are in the weekend, I only have a picture for the VI, now.  But I will do my best to provide you the VI after few hours.

By tha way I think that I did mistake in the VI, especially in the division Ithink that I reversed the terms (see the file below). Another Thing, I Tried to change the loop timer from 500 to 1000 ( to test if somethings will change but it's seems that the problem persists), also after this I change the value of timed out from 0 to -1 ( to retrieve all the data ) but no change

Kind regards

Rira

[rira18]

Hi T-Rex$,

Please find in the attachements, the VI's for DMA block diagram (FPGA and host) and I will send you the VI of Ni example after 1 hours

Thank you very much

Kind regrads !

Rira

[rira18]

Hi T-Rex$,

Please find in the attachement, the VI Ni example.

Please help me I'm lost and I didn't know what to do

I found that only one acquisition work correctly, When I entered a sinus signal, or square I found it in the graph but for the second input I just found a signal in the high amplitude: I found only tha square signal but the sinus had only one alternance.

By the way I used AI2 and AI3 in the SCB-68 connector, I changed the wire but the problem still

Pleaaaaase help me

[T-REX$]

Hello rira18,

It looks like you are railing at 10V. I suspect that you have a grounding issue in your setup somewhere causing this. For wiring issues I usually recommend this article. What type of signals are your bringing in? Are they ground referenced or floating?

[rira18]

Hi T-Rex$,

I saw the article what you refered to me and I understood that I have to connect the GND, but when I talk about this to my supervisor he said to me that GND is automated wired in the internal way !

That's way, I send you the pictures of my connection, I used connecrtor0/AI2 and  connecrtor0/AI3 to acquire the same signals

Please help me please

Kind regards

[T-REX$]

Hello rira18,

Another possible cause of the railing seen in the images that you sent over is that a DC offset is introduced into them somehow. The easiest explanation for this would be that the DC component from your signal generator (usually adjustable) is not 0. I see that your function generator has a DC offset knob. If you adjust it (pull it down), do you still see the railing?

[rira18]

Hi T-REX,

I hope you are fine,

Sorry for this late to reply but I just find the problem. It was because that the connector 0 I3 didn't work, I change it to the connector 0, I0 and it's work perfectly. Really thank you very much for all your help.

Now I found another problem, with the LMS. when I tried to use the LMS, the system indicate me that there is a problem with length. I find the link which indicate how to generate FPGA code for LMS, I remplaced the "joint numbers" by the LMS which I generate it following this link: http://zone.ni.com/reference/en-XX/help/372357A-01/lvaft/aft_db_codegen/
But the complilation is failed (please see the document bellow)

Which modification do I have to make? Do I have to adapt the example about the to adaptive noise cancellation which I find in LabView?

Please if yoy can help me don't hesitate because i have to present my work the next week.

Thank you very much

Best regards

Rira

[T-REX$]

Hi rira18,

If that word document shows the only FPGA code running on your controller, that is very supprising. How large is that FIFO? The error that you got shows that you are using up twice the resources that are available on your device. Looking at the error, I would guess that the FIFO you have there is enourmous, and implemented in FLIP-FLOPS or LUTS rather than Block RAM. I would first try implenting in Block RAM, then if you still have errors, reduce the size of the FIFO, and read faster on the host side.