Finite Sample Acquisition with FPGA (Timing Question)

[atomtrainers]

I'm trying to acquire a finite number of samples (10000) at a given rate (1kHz) with my PXI7853R card. I had previously used a USB DAQ and simply used the DAQmx NChan, NSsamp vi. Very straightforward stuff. However, I'm finding things much more difficult in FPGA Land, where I am very inexperienced.

I found an example for continuous sampling and modified it to what I was hoping would fit my needs. Both the FPGA and Host files are attached, and I included some screenshots as well. The BigData FIFO has the following properties: Target to Host DMA, 8191 elements, U32 data type.

The problem I'm having is with timing. Acquiring at 1kHz means setting the "tick" timer of the FPGA to [40MHz/1kHz] = 40000 ticks. However, when I run the code, the "actual" ticks reads 75, and the measurement is completed in less than a second, rather than the [10000 Samples / 1000 Samples/s] = 10 s. I seem to have no control over how fast this process runs. I do end up with 10,000 samples. But the information is useless since the time axis is incorrect.

Any ideas why this is happening?

Thank you very much in advance.

Zack

[thoult]

Can't open at home to see (only have 2012 here, 2013 at work), but why are you configuring the loop timer after you've started acquiring data,filled the FIFO and then read out from it?

Will have another look tomorrow.

[atomtrainers]

Thanks for the reply. The ordering of the configurations just came from the example program that I found here: http://www.ni.com/tutorial/4534/en/ 

Perhaps because I'm no longer in a while loop, I should do the timing first. I rearranged the code in a sequence structure (attached) but now I can't get any data...only an error code

-50400: Invoke Method: FIFO.Read in hostread1shot.vi

I'll keep trying, but appreciate you looking over it!

Zack

[atomtrainers]

Alternatively, if someone has FPGA/Host code that acquires finite samples at a fixed rate, I'd be perfectly happy to throw away my crap and use yours! 🙂

[thoult]

I've no way of testing this with your code, but you have Open FPGA VI Reference set to Run, then configure the FIFO, then start the FIFO. But on the FPGA, as soon as it runs, it'll start filling elements into the FIFO, so you might notice that either it overflows quickly at the beginning or you have additional data you didn't actually want it to acquire.

For finite sampling, I tend to have FPGA code that looks something like this:

 

Ignoring the pipelining and all the other guff that's going on that's irrelevant to you, I have my FIFO Write in a case structure with a Boolean wired to the input. That means I only start loading samples into my FIFO when I want to. On the RT, I first configure the host side of my FIFO, start it and then when I want to start filling it I set that Boolean on the FPGA to true and read out for as many samples as I wish. When done, I set the Boolean to false, and flush the FIFO by reading all available elements from it.