Generating FPGA Clock betewen (50KHZ - 800 KHZ)

[Emna20]

Hi,

I am using cRio 9068 + NI 9401+  SPI Sensor Pressure . In FPGA mode, I want to generate a clock of 800KHZ. but the Frequency of FPGA mode is 40MHZ . can anyone help me.

Best Regard.

[Terry_ALE]

You need to make a derived clock.  See: https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgahelp/creating_fpga_derived_clk/

[Emna20]

Hi,

i Could not change the FPGA clock Under 40MHZ. can anyone help me .

Best Regard.

[GerdW]

Hi Emna,

you could create a derived clock from the FPGA base clock in your project - but this will only allow down to 4.69MHz for this cRIO type (tested with cRIO9066).

But you can create a SCTL in your FPGA VI, running at 40MHz. This SCTL can then switch a boolean flag each 50 iterations to create your 800kHz clock signal!