Hardware Timed Single Point Data Acq with PCI-6143

[Ryan_V[DE]]

Ryan,

Are you consistently missing the same point, or is the location and / or occurrence of the missing pulse random? Also, did you try Micaela's suggestion of modifying a shipping example to use timing from the RTSI bus?

Thanks,

[RVallieu]

It is not always the same point in the array.

I am using the RTSI bus to route the signal from the FGen to the S-DAQ.

[Ryan_V[DE]]

Ryan,

Could you post the smallest amount of code that exhibits this behavior? We will look into it on this end.

Thanks,

[RVallieu]

I figured out with the help of a coworker that it was a memory allocation and handling issue.  When I was using shift registers in my one loop of my validation test vi it was missing points.  When I created another vi and used queues to transfer the data to a data handling loop, reduced the data and stored it, then discarded it from memory - I did not miss any points.

[Ryan_V[DE]]

Ryan,

Glad to hear you got it working. Good luck with your application!

Regards,