How can I get my CLIP working?

[TomC_NGC]

I'm trying to figure out how to use CLIP with Labview FPGA 8.6.

I've created a small vhdl file and matching xml file. For some reason, simulation shows the output vector as random data. Output is stuck at zero when I run it on my PXI-7811R.
I wonder if my link to the vhdl file within the xml file is invalid?

I tried following the tutorial, and I'm pretty close, but something is not quite right.

[Ray.R]

I took the course a while ago..  So it's a bit far in my mind.,.

The image you posted looks like there might be a race condition.  Can you write to "Component Level IP\value_in" after reading "Component Level IP\value_out"? Because there is no flow of data in your While Loop.  Also, should there be a reference wired to the two nodes?

R

[TomC_NGC]

Originally I had a register/flip-flop in my vhdl file, which should eliminate any race conditions. At least, that's how I would normally do things.

Register made no difference.

I don't think I need any special linking to use the CLIP I/O.

Message Edited by TomC_NGC on 10-08-2008 07:19 AM

[RyanB]

Hi Tom,

I'm glad to see you are trying out the CLIP feature of LabVIEW 8.6.  It sounds like you have 2 questions:

1 - Why does my CLIP produce random data in simulation?

2 - Why does my CLIP produce no data when running in hardware?

Regarding #1 - By simulation I assume this means you have selected "Execute VI on Development Computer with Simulated I/O" in the Debugging tab of the FPGA Target Properties menu.  In this mode CLIP I/O will produce either random data or data from a VI you specify (also configured in the same menu).  Therefore, if you would like more realistic I/O data in your simulation, you must write a VI to generate this data.

Note - Some targets allow you to connect data from Real I/O to your simulated FPGA VI.  However, this capability does not exist for CLIP I/O.

Regarding #2 - I looked at your CLIP files briefly and I noticed one problem - the reset signal in your CLIP VHDL is active low.  The reset signal from LabVIEW FPGA is active-high.  This means when running in hardware your CLIP will be held in reset.  Try inverting the reset in your CLIP VHDL (i.e. if reset = '1'...).  I will review our documentation - we may need to make this reset polarity more clear in the documentation.

Best regards,

RB

[TomC_NGC]

I tried it this time, using an active high reset and flip-flops. It worked.

Lesson Learned: Always use an Active High reset in your CLIP.