How fast can I sample with my sbRIO DIOs- FPGA

[XM43]

Hi,

I am using sbRIO 9638 and I utilize FPGA to communicate with some sensors. A recent application forced me to use derived clock of 100Mhz. This made me questions, how fast can a DIO be sampled? Are DIOs actually being sampled at 100 Mhz or they are maxed out at the base frequency?

I have been unable to get a concluding answer after referring to specification sheet  and Xilinx's product selection guide.

I would appreciate if someone could educate me on this. From my understanding DIOs can be sampled as fast as FPGA is running. But higher the Mhz higher the jitter? But not sure.

[GerdW · Accepted solution]

Hi x,

in the specsheet the highest frequency value for anything related to DIO is 20MHz...

In my memory I had the value of 40MHz for DIO pins of the FPGA..

[XM43]

Hi GerdW,

Please correct me if I am wrong. If the highest frequency for DIO is 20 Mhz then my shortest possible bit width would be 50ns?

But I am able to send out signals at 40, 80 and 100 Mhz with 25, 12.5 and 10 ns of minimum bit width. This confused me, I think I am missing out on something fundamental here. 😕