Hi Durnek,
I took a look over your code and I have a few questions.
First of all, it may be useful to create a timing benchmark of how much time it takes for the RT controller to write a U8 scalar to a DMA and to read it back from the second DMA. This is optional, and it can help in the way that you can create a more efficient DMA transfer framework without dealing with 2-dimensional arrays and IMAQ functions. You can then build your code from there and know how long your VIs execution should last.
The second issue has to do with dataflow. CompactRIO controllers have only one processor (with 1 core) and therefore can only execute one task at a time. It looks like the VI has created a race condition between DMA reading (While loop) and DMA writing (For loop). My questions are:
Does the For loop that writes data execute before or after the While loop that reads data?
What rate does the For loop execute at?
This is important especially since the DMA Target to Host FIFO Read method is polling - Timing with DMA Target to Host FIFO Read method.
You can consider using a Timed Loop, decide which of your loop has higher priority and allow time between iterations of the higher priority loop for the second loop.
After going through the material and finding out more about your code's execution, please let me know of your questions and progress.
Have a great day,
Patricia
